PYNQ: PYTHON PRODUCTIVITY

PYNQ Z1 axi stream without side band

i am using PYNQ Z1 board and vivado Hls for simple axi4 stream interface implementation.
i am just sending an array[50] from DDR to stream through DMA and try to receive back on DDR using HP0 port ZYNQ. i am not able to get back data complete. while receiving from DMA i am losing even number of indexes .

from PS to PL
[ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
48 49]
from PL to PS
[ 0 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 16 0 18 0 20 0 22 0
24 0 26 0 28 0 30 0 32 0 34 0 36 0 38 0 40 0 42 0 44 0 46 0
48 0]

The symptoms look like the result of a mismatch of AXI port widths. You need make sure the width of the HP0 port in Vivado is set to 64 bits.

Peter