Sure. I was in the midst of re-implementing the design with changes I thought might help (they didn’t) and a system ILA (which prevents using PYNQ, it seems because I’d never set cpuidle.off=1 in uenv.txt, per this other post).
I’m on the ZCU111, PYNQ 2.5, using 2019.2 for all my work and clocking at 100MHz (for testing, eventually the streams must be at 512MHz, but then I won’t be working with a DMA!). My test bench block diagram is:
And some of the key points are:
.
In case it becomes relevant the HLS core’s code/docs are here. I don’t have the Python testbench into a public git yet.