Using MMIO with custom HDL

[matthew]

Hi,
Is this request similar to this one?

Sending data to custom IP and receiving it back

Hi, I have written some hdl code that takes in 9 32 bit integers, performs some data processing on them, including things like finding the mean, variance etc, then after a couple of clock cycles, a valid signal is set high I can read 18 32 bit integers from the outputs of my logic, written in System Verilog. This all works in simulation, but now I want to run it on my PYNQ Z1 board, however, I have no idea how to send data from the pynq PS to the PL where my logic would be and then read the ou…