I have written some hdl code that takes in 9 32 bit integers, performs some data processing on them, including things like finding the mean, variance etc, then after a couple of clock cycles, a valid signal is set high I can read 18 32 bit integers from the outputs of my logic, written in System Verilog.
This all works in simulation, but now I want to run it on my PYNQ Z1 board, however, I have no idea how to send data from the pynq PS to the PL where my logic would be and then read the outputs again when i set the valid signal in my logic.
Any help/ tutorials on this would be greatly appreciated.
Yopu could also use a Direct Memory Access block to enable the communication betweeen PS and PL. Maybe you can find more details here: Tutorial: PYNQ DMA (Part 1: Hardware design)
I thought about using MMIO, however, how do I verify that I read the output registers/ memory addresses when my valid from my custom hardware is set high?
Your PS could send the 9 integers to the PL to specific registers. The PS could then check another register containing the valid indicator. When this indicator has a high value, the PS could read from the 18 registers of the integers.
Could this be possible?
