PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

Using PL DDR4 MIG IP

Has anyone try to use the PL DDR4 MIG IP to control the DDR4 SODDIM memory? I have a ZCU104 board and I try to create a block diagram that I will allow me to control the DDR4 SODDIM memory from the PS side. I was wondering what is the setup necessary for this to work.

This doesn’t seem to be related to PYNQ. You would be better posting this to the main Xilinx forum:

Cathal