Hello,
I am trying to re-create the PYNQ base project and modify it to see how Vivado and PYNQ interact. I have the following question:
1- What do iop_mode0 and ip_mode1 do IP block do?
2- I have build the project using the tcl script and tried to implement it but I get this errors
-[Mig 66-99] Memory Core Error - [base_i/ddr4_0] Either port(s) c0_sys_clk_p, c0_sys_clk_n is/are not placed or un-supported clocking structure/circuit for memory ip instance. Please refer to clocking section of PG150 for supported clocking structures.
[Mig 66-99] Memory Core Error - [base_i/ddr4_0] Port(s) ddr4_pl_ck_c[0],ddr4_pl_ck_t[0],ddr4_pl_adr[0],ddr4_pl_adr[1],ddr4_pl_adr[2],ddr4_pl_adr[3],ddr4_pl_adr[4],ddr4_pl_adr[5],ddr4_pl_adr[6],ddr4_pl_adr[7],ddr4_pl_adr[8],ddr4_pl_adr[9],ddr4_pl_adr[10],ddr4_pl_adr[11],ddr4_pl_adr[12],ddr4_pl_adr[13],ddr4_pl_adr[14],ddr4_pl_adr[15],ddr4_pl_adr[16],ddr4_pl_ba[0],ddr4_pl_ba[1],ddr4_pl_bg[0],ddr4_pl_cs_n[0],ddr4_pl_cke[0],ddr4_pl_odt[0],ddr4_pl_act_n,ddr4_pl_reset_n,ddr4_pl_dqs_c[0],ddr4_pl_dqs_t[0],ddr4_pl_dm_n[0],ddr4_pl_dq[0],ddr4_pl_dq[1],ddr4_pl_dq[2],ddr4_pl_dq[3],ddr4_pl_dq[4],ddr4_pl_dq[5],ddr4_pl_dq[6],ddr4_pl_dq[7],ddr4_pl_dqs_c[2],ddr4_pl_dqs_t[2],ddr4_pl_dm_n[2],ddr4_pl_dq[16],ddr4_pl_dq[17],ddr4_pl_dq[18],ddr4_pl_dq[19],ddr4_pl_dq[20],ddr4_pl_dq[21],ddr4_pl_dq[22],ddr4_pl_dq[23],ddr4_pl_dqs_c[3],ddr4_pl_dqs_t[3],ddr4_pl_dm_n[3],ddr4_pl_dq[24],ddr4_pl_dq[25],ddr4_pl_dq[26],ddr4_pl_dq[27],ddr4_pl_dq[28],ddr4_pl_dq[29],ddr4_pl_dq[30],ddr4_pl_dq[31],ddr4_pl_dqs_c[4],ddr4_pl_dqs_t[4],ddr4_pl_dm_n[4],ddr4_pl_dq[32],ddr4_pl_dq[33],ddr4_pl_dq[34],ddr4_pl_dq[35],ddr4_pl_dq[36],ddr4_pl_dq[37],ddr4_pl_dq[38],ddr4_pl_dq[39],ddr4_pl_dqs_c[5],ddr4_pl_dqs_t[5],ddr4_pl_dm_n[5],ddr4_pl_dq[40],ddr4_pl_dq[41],ddr4_pl_dq[42],ddr4_pl_dq[43],ddr4_pl_dq[44],ddr4_pl_dq[45],ddr4_pl_dq[46],ddr4_pl_dq[47],ddr4_pl_dqs_c[6],ddr4_pl_dqs_t[6],ddr4_pl_dm_n[6],ddr4_pl_dq[48],ddr4_pl_dq[49],ddr4_pl_dq[50],ddr4_pl_dq[51],ddr4_pl_dq[52],ddr4_pl_dq[53],ddr4_pl_dq[54],ddr4_pl_dq[55],ddr4_pl_dqs_c[7],ddr4_pl_dqs_t[7],ddr4_pl_dm_n[7],ddr4_pl_dq[56],ddr4_pl_dq[57],ddr4_pl_dq[58],ddr4_pl_dq[59],ddr4_pl_dq[60],ddr4_pl_dq[61],ddr4_pl_dq[62],ddr4_pl_dq[63],ddr4_pl_dqs_c[1],ddr4_pl_dqs_t[1],ddr4_pl_dm_n[1],ddr4_pl_dq[8],ddr4_pl_dq[9],ddr4_pl_dq[10],ddr4_pl_dq[11],ddr4_pl_dq[12],ddr4_pl_dq[13],ddr4_pl_dq[14],ddr4_pl_dq[15] is/are not placed. Assign all ports to valid sites.
- [Opt 31-306] MIG/Advanced IO Wizard Cores generation Failed.
Any idaea what is wrong?
Thanks,
Cherif