Vitis library crop function kria SOM kv260

Hello all,

I’m beginner to use vitis hls/vitis vision library. Really thanks everyone who can open this question and who can give me some guide! Now I’m trying to implement the crop IP from vitis library. I have done a little change to the code to do some practise.

#include "hls_stream.h"
#include "ap_int.h"
#include "common/xf_common.hpp"
#include "common/xf_infra.hpp"
#include "common/xf_utility.hpp"
#include "imgproc/xf_duplicateimage.hpp"
#include "imgproc/xf_crop.hpp"
#define DATA_WIDTH 24
#define NPIX XF_NPPC1
/*  set the height and width  */
#define WIDTH 362
#define HEIGHT 182
#define FILTER_SIZE 3
#define TYPE XF_8UC3
#define NUM_ROI 1
void crop_pgl_accel(
    ap_uint<DATA_WIDTH>* src, ap_uint<DATA_WIDTH>* dst, int rows, int cols, int* roi) {
#pragma HLS INTERFACE m_axi     port=src  offset=slave bundle=gmem0
#pragma HLS INTERFACE m_axi     port=dst  offset=slave bundle=gmem1
#pragma HLS INTERFACE m_axi     port=roi   offset=slave bundle=gmem2
#pragma HLS INTERFACE s_axilite port=rows     
#pragma HLS INTERFACE s_axilite port=cols   
#pragma HLS INTERFACE s_axilite port=return
    printf("started loading rect execution\n");
    xf::cv::Rect_<unsigned int> _roi[NUM_ROI];
    for (int i = 0, j = 0; j < (NUM_ROI * 4); i++, j += 4) {
        _roi[i].x = roi[j];
        _roi[i].y = roi[j + 1];
        _roi[i].height = roi[j + 2];
        _roi[i].width = roi[j + 3];
    xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPIX> in_mat(rows, cols, src);
    xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPIX> out_mat(_roi[0].height, _roi[0].width,dst);
    xf::cv::crop<TYPE, HEIGHT, WIDTH, MEMORYMAPPED_ARCH, NPIX>(in_mat, out_mat,_roi[0]);

I also write a script for hls:

set vitis_lib_include [lindex $argv 2]
open_project crop_pgl_accel
set_top crop_pgl_accel
add_files crop/xf_crop_pgl.cpp -cflags "-I../../Vitis_Libraries-2022.2/vision/L2/include -I../../Vitis_Libraries-2022.2/vision/L1/include  -D__XF__AXI_SDATA__ -D __SDA_MEM_MAP__"
open_solution "crop_pgl" -flow_target vivado
#set_part {zynq}
set_part {zynquplus}
create_clock -period 10 -name default
set_clock_uncertainty 27.0%
#Synthesize and export IP using Vivado flow
config_export -format ip_catalog -rtl vhdl
export_design -format ip_catalog -description "Image crop IP - PGL" -display_name "crop_pgl_accel"

The system I created is here:

I tried to run this in pynq plateform and unfortunately all I got is a black image as output…
pipo_sys.ipynb (344.7 KB)

I have already implenmented a lot of others IPs version core with AXI stream/stream type kernel, but this is my first time to use AXI memory mapped/memory mapped type kernel. I haven’t find much tutorial about this subject… Thanks again for any poosible answers to this questions!!