PYNQ: PYTHON PRODUCTIVITY

Vivado 2019.2 HWH parser issue

Hello,

I am trying to create an overlay containing my custom IP.

However, I get the following error:AttributeError: 'NoneType' object has no attribute 'get'
at line: mod = it.find(".//PORTS//*[@DIR='I']" "//*[@INSTANCE='{0}'][@PORT='{1}']../../../..".format(self.ps_name, self.family_gpio)) of the hwh_parser.py.

Looking online,I have come accross a few posts referring to some issues regarding the hdw/tcl parser with Vivado 2019.2 version.

How can I understand whether it is a parsing issue or anything is wrong with my design? The bitstream generation was successfully (?) completed without any errors.

Thank you,
Sam

This might be because of the changes in 2019.2 HWH file. We are currently working towards the next release.

Maybe you can port over your project back to 2019.1 and see if HWH parser works? Otherwise we will have to wait until we are testing our next release.

Hello, I tried implementing the same design with Vivado 2018.3 and although the bistream generation completes successfully I still get an empty IP dict when using the .tcl file or the error: AttributeError: 'NoneType' object has no attribute 'get' at line: din = int(mod.find(".//*[@NAME='DIN_FROM']").get('VALUE')) of the self.add_gpio() function in the overlay.py script when using the HWH file. Could you please help me figure out what’s causing this issue? Thank you.

Can you send a copy of your Tcl, and an image of your block diagram?

Cathal

Hello @cathalmccabe,
sorry for the late reply.

I solved the issue using Vivado 2018.3.

It seems like using the .tcl and .bit file from the HDL wrapper bitstream generation does not work. Using the .bit file from the HDL wrapper bitstream generation and the “export hardware” .tcl file works.

What I mean by that, for example, is that is your HDL wrapper is “a_wrapper”, using a_wrapper.bit and a_wrapper.tcl does not work. But using a_wrapper.bit and a.tcl (renamed to match the .bit file), it works.

Sorry if I am saying something obvious, I am a new to FPGA design.

Thank you for your help.

Sam