Vivado Heirarchies with Zynq processing system

I’m using a Pynq Z2 with the 3.08 software version. Vivado 2023.1 tools. The Vivado project uses the IP blocks for the Zynq7 Processing system, Processor System Reset, and AXI Interconnect. Additionally, I’ve included a Clocking Wizard and a few custom IP blocks to capture my behavior. To clean up the Vivado interface, I’ve made a hierarchical element that contains the Zynq processing system, Reset, and AXI interconnect IP.

The Vivado project synthesizes and implements, and generates the bitstream with no errors. However, when I attempt to interact with it from the Jupyter Notebook (JN), I get the errors shown in the code snippet at the bottom of this post (for an overlay called ‘Adss_1_2.bit’.

I’ve noticed that if I don’t group those 3 mentioned items into a hierarchical element, I can interact with the hardware from the JN as expected. I did see a note on one of the Pynq documentation pages (int he PS section of that page) suggesting… ‘The Zynq PS is also supported within a hierarchy, but this is discouraged.’ with no other reason given. It would be nice to be able to include it in a heirarchy. Can anyone please suggest a way to do it?

KeyError                                  Traceback (most recent call last)
Input In [5], in <cell line: 2>()
      1 from pynq import Overlay
----> 2 ol = Overlay("Adss_1_2.bit")
      3 get_ipython().run_line_magic('pinfo', 'ol')

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/, in Overlay.__init__(self, bitfile_name, dtbo, download, ignore_version, device, gen_cache)
    345     self.systemgraph = None
    347 if download:
--> 348
    349 else:
    350     if gen_cache:

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/, in, dtbo)
    425         else:
    426             Clocks.set_pl_clk(i)
--> 428 super().download(self.parser)
    429 if dtbo:
    430     super().insert_dtbo(dtbo)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/, in, parser)
    151 def download(self, parser=None):
    152     """Download the bitstream onto PL and update PL information.
    154     If device tree blob has been specified during initialization, this
    167     """
--> 168, parser)

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/, in, bitstream, parser)
    681 with open(self.BS_FPGA_MAN, "w") as fd:
    682     fd.write(bitstream.binfile_name)
--> 684 self.set_axi_port_width(parser)
    686 self._xrt_download(parser.xclbin_data)
    687 super().post_download(bitstream, parser,

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/, in EmbeddedDevice.set_axi_port_width(self, parser)
    617 if not hasattr(parser, "ps_name"):
    618     # Setting port widths not supported for xclbin-only designs
    619     return
--> 620 parameter_dict = parser.ip_dict[parser.ps_name]["parameters"]
    621 if parser.family_ps == "zynq_ultra_ps_e":
    622     for para in ZU_FPD_SLCR_REG:

KeyError: 'ProcSubSystem_processing_system7_0'