Which vivado IP block is required to transfer data to and from a kernel?

Hi there,

I created a kernel with vitis_hls (2020.2) for a PYNQ-Z1 board. As I understand (but I might be wrong), there is no way to create an xclbin with vitis for this board, which implies that the process to create the bitstream (.bit) has to be done manually, with vivado.

When using pynq to communicate with the kernel, the methods call, sync_to_device are not available, as they are available only for xclbin designs (am I right?).

This implies in turn that one has to use the dma module (e.g., dma.sendchannel.transfer). According to the documentation, this module supports the AXI central DMA IP.

My m_axi ports have the interface shown in the picture. Which vivado IP should I use in the block diagram interconnection to transfer data to and from my kernel? It seems I can only connect my kernel to an AXI multichannel DMA, which seems not to be recognized by pynq.

Thanks in advance,


Yes, you need a .bit for Pynq-Z1. XCLBINs are for Alveo/AWS.
Yes, call sync_to_device aren’t needed for Zynq designs as the memory is cache coherent.

I’ll give you some background on your question about your IP, in case this is new to you.

AXI interfaces

When creating IP with AXI interfaces, you can create Masters or Slaves (The can be AXI (full), AXI Lite, or AXI stream, and each of these can be a masters or a slaves, so there are 6 different options in total. Ignore the port type for now, and considering only Masters and Slaves;


A DMA, is an offload engine, to avoid requiring your CPU to do large data transfers. It will get a source address and a destination address and do the memory transfer. The CPU could do this. You could write a loop in software to read from one place, write to another. You can do this, but it isn’t an efficient use of CPU cycles.


If your IP had a slave interface, and you want to read or write a lot of data to/from your IP over this interface, you could connect this interface to the DMA. The DMA will have Master interfaces to connect to the Slave on the IP. The DMA can repeatedly read from your IP and write the data to the destination, or read from the data source, and write the data to your IP.


In the image you posted, you have an AXI MASTER port. AXI master ports can initiate AXI transactions on their interface. i.e. they can carry out a read or a write transaction. Masters connect to Slaves, so on the Slave side that interface waits for, and responds to a Master transaction.

Say your IP wants to read or write large amounts of data from memory, it can be connected directly to a Slave port of the memory and do this automatically and no DMA is required.

IP setup

You will need to do some setup of your IP. The Master address will read/write and address. At a minimum, you need to pass the address to the IP. There should be another AXI Slave on your IP, and a specific register for the address.
You usually need to “start” the IP, by writing a start bit to another register which might be mapped to the same AXI Slave interface as the address for the AXI master. You would normally share a single AXI slave interface for these types of control registers, but it is possible to have separate interfaces for this.
Depending on your IP, there may be other things needed to setup the IP.

If you are new to FPGA, you may have lots of questions at this point. You may be better going back to some tutorials, documentation or other training or just doing some more reading about some of these topics.

Some more info:


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Thanks @Cathal for the very comprehensive answer. I was not aware of the difference between master and slave on the IP side, and was inadvertently using m_axi instead of axis.

Is the Vitis flow (i mean what you do for Alveo/AWS) eventually gonna be supported for this kind of boards (i.e. PYNQ-Z1)?


There is no hw project for PYNQ-Z1 in Petalinux or PYNQ build directory?