Hello,
Thanks for your answer. Meanwhile, I also reached out to TI Forum and got support there as well.
Posting the Reply from TI support in case it helps someone else with the same problem:
Are you testing this with an evaluation module? If so, can you tell me whether the LEDs indicate lock for both PLLs? As I imagine it, the LED corresponding to PLL2 should be lit up, and the LED corresponding to PLL1 should not. This is behaving as expected. PLL2 is turned on because the output of the external VCXO (160 MHz) is phase synchronized with the frequency of the on board VCO (3000 MHz). It will generate an output even without an input. However, your intended use is to make the phase relationship between the input and output of the device deterministic - which can only be achieved if you drive the input with the specified 10 MHz signal. *
If you do not want an output signal, set the corresponding clock outputs to powerdown mode.
So, in my case the board is CLK104 from Xilinx. I confirmed that PLL1 of LMK was not locked as long as the external ref clock was not provided via the SMA. The PLL1 was locked once the ref clock was supplied. The on-board LEDs on CLK104 can be used to verify this behavior and this is inline with what is explained above(TI Forum reply).
regards
Ponnanna