I’ve got a RFSoC design based on the Xilinx Multi-Tile Synchronisation example design. I’m not sure how to go about initialising the rfdc component. When I load my overlay and interogate it I see the rfdc component has been given the DefaultIP driver rather than the xrfdc driver I hoped for.
From the docs here:
It states that " The class
RFdc is bound to the IP
xilinx.com:ip:usp_rf_data_converter:2.4 . Once the overlay is loaded, the data converter IP will be allocated the driver code implemented in this class."
My design was built with a later version of the Xilinx tools (2021.2) rather than 2020.2 that matches the PYNQ release. The usp_rf_data_converter is at version 2.6 in my design. Could that be why the driver hasn’t been associated correctly?
Yes, the version mismatch is likely. Did you get a warning related to this?
You can try pass
ignore_version=True to the Overlay class (by default this is
False) to try and workaround. If you are not seeing a warning then I don’t think this is the issue.
Just to add, I’m sure you realise that with unsupported/untested IP versions you may run into other issues.
Hi @cathalmccabe - I rebuilt the design for 2020.2 but it still gave me the same DefaultIP driver. After a quick bit of googling I stumbled across:
Which said “the first thing which is imported is the new xrfdc package. Before applying the overlay containing the PL design”
So if I first do:
Prior to applying the overlay:
from pynq import Overlay
ol = Overlay("./mts_ex_des.bit")
So that looks more promising.
Just as an update. With the xrfdc package imported prior to loading the overlay with my 2021.2 build I do see this warning regarding the usp_rf_data_converter:
The IP block then gets assigned the DefaultIP driver again.
If I pass the ignore_version=True argument as suggested by @cathalmccabe, then this warning disappears and the RFdc driver is assigned to the usp_rf_data_converter.