PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

RFSoC DAC with Pynq

Hello,

I am working with a firmware that uses the DAC on the ZCU111 RFSoC board. I have done a very simple design and tested it in bare metal. It has a counter feeding a DAC. It works in bare metal.

When I move to Pynq, it seems like I am able to load the .bit and read the .hwh file with the Overlay class. I can list the IPs and other stuff.

However, the DAC does not work. I have a couple of questions:

  1. In bare metal, the bitstream contains the configuration of the DAC tile. It does not seem to be the case when loading the bitstream using the Overlay class. Is this correct?
  2. I see there’s a library called xrfdc but I could not find a simple example on how to use it. I would like a very simple one, just configuring and using one simple ADC/DAC tile.

Thank you in advance,

The University of Strathclyde have an example design that uses the DAC and ADC blocks in a complete QPSK system. You can find it here.

Peter

The configuration of the DAC block should be contained within the hwh file and the xrfdc library should automatically configure itself from that - if not there is a bug somewhere.

Peter

Hi Leandro,

Just adding to Peter’s comments. Sounds like the DAC block might not be getting clocked correctly. Things to look out for:

  1. Remember to configure any LMK/LMX clocks that you use - the DAC won’t
    work without its reference clock. We’ve got a simple driver called xrfclk
    for this.
  2. If you use the DAC tile’s internal PLL, call the DynamicPLLConfig function.

Something like the following lines might be enough to get you up and running:

from pynq import Overlay
import xrfclk

ol = Overlay("my_bitstream.bit")

# Set up RF refrence clocks
xrfclk.set_all_ref_clks(409.6)

# Optionally set up DAC tile's PLL
dac_tile = ol.usp_rf_data_converter_0.dac_tiles[YOUR_TILE_NUM]
dac_tile.DynamicPLLConfig(1, 409.6, 1228.8)

I agree that a very simple data converter demo would be useful, especially
for folks interested in instrumentation rather than comms. If you are in a
position to open source your counter design, perhaps this could become a good
example design?

Cheers,
Craig

Hi Craig,

Thank you all guys for your answers. One day after uploading the problem, I found the external PLL was not giving me the frequency so I fixed that and the example is working now.

I can share the project with you, it is just a counter with the only interesting thing that it has a “parellel” implementation, so that all outputs of the AXI Stream are driven to properly count at the maximum frequency of the DAC.

Regards,
Leandro