I am working with a firmware that uses the DAC on the ZCU111 RFSoC board. I have done a very simple design and tested it in bare metal. It has a counter feeding a DAC. It works in bare metal.
When I move to Pynq, it seems like I am able to load the .bit and read the .hwh file with the Overlay class. I can list the IPs and other stuff.
However, the DAC does not work. I have a couple of questions:
In bare metal, the bitstream contains the configuration of the DAC tile. It does not seem to be the case when loading the bitstream using the Overlay class. Is this correct?
I see thereâs a library called xrfdc but I could not find a simple example on how to use it. I would like a very simple one, just configuring and using one simple ADC/DAC tile.
The configuration of the DAC block should be contained within the hwh file and the xrfdc library should automatically configure itself from that - if not there is a bug somewhere.
Just adding to Peterâs comments. Sounds like the DAC block might not be getting clocked correctly. Things to look out for:
Remember to configure any LMK/LMX clocks that you use - the DAC wonât
work without its reference clock. Weâve got a simple driver called xrfclk
for this.
If you use the DAC tileâs internal PLL, call the DynamicPLLConfig function.
Something like the following lines might be enough to get you up and running:
from pynq import Overlay
import xrfclk
ol = Overlay("my_bitstream.bit")
# Set up RF refrence clocks
xrfclk.set_all_ref_clks(409.6)
# Optionally set up DAC tile's PLL
dac_tile = ol.usp_rf_data_converter_0.dac_tiles[YOUR_TILE_NUM]
dac_tile.DynamicPLLConfig(1, 409.6, 1228.8)
I agree that a very simple data converter demo would be useful, especially
for folks interested in instrumentation rather than comms. If you are in a
position to open source your counter design, perhaps this could become a good
example design?
Thank you all guys for your answers. One day after uploading the problem, I found the external PLL was not giving me the frequency so I fixed that and the example is working now.
I can share the project with you, it is just a counter with the only interesting thing that it has a âparellelâ implementation, so that all outputs of the AXI Stream are driven to properly count at the maximum frequency of the DAC.
I am asking my question in reply to this post since it is very related. I hope someone can help me.
I am using the DAC on the ZCU111 RFSoC board and I am using pynq. I am trying to update the mixer setting using xrfdc lib. First, I can get the initial setting as:
ol = Overlay(âmy overlayâ)
ol.dac_block.MixerSettings
Thanks for the response. I manage to update the settings using the second way that you recommended. This way, once can define multiple PLL settings and use them.
How would it be possible to configure LMK/LMX for other freq options through pynq? As far as I am concerned, by using âset_all_ref_clksâ command, only the values from âget_freq_listâ are allowed and for other freq options, one would need to use _write_lmk04208_regs() and _write_lmx2594_regs() functions with the register values.
Do you have an example that shows how to use those functions for other freq options? Specifically, I want to set the DAC reference clock to be integer multiple of 122.88 MHz.
I have had exactly the same problems. Except I have been unable to fix the external PLL ( the LMX2594 PLL ) . In baremetal mode ( i.e. using the SDK drivers ) the xrfdc/xrfclk drivers seem to be able to reprogram the LMX2594 PLL . However using PYNQ I cannot get the drivers to start the LMX2594 PLL ) . You seem to have fixed this - can you help me!