You shouldn’t need to change the port from 0.0.0.0 - that will bind to all network interfaces. In theory - yes changing the port and assigning the correct IP to the debug_bridge variable all that should be be required. If you are on a Zynq Ultrascale+ board you may also need to do the cpuidle fix to prevent the processor from locking when the JTAG chain is accessed. Note that it may not be particularly quick. This was put together as a proof of concept rather than something production ready.
Peter