Using the DebugBridge to visualize an ILA in Vivado


I’m currently trying to debug my design using the Internal Logica Analyzer (ILA) IP within my design. From both the PYNQ and AMD documentation, it seems that for boards which are using an Ethernet connection with the PS one needs to add two IPs: a debug bridge from my logic (in this case I’m using the AXI to BSCAN) and a second debug bridge to the debug hub.

I implemented it in my design and then tried to launch the xvc server from PYNQ, using the following line:

cl.debug_bridge_0.start_xvc_server() # cl is the name of the Overlay instance

but I get the following stack trace:

RuntimeError                              Traceback (most recent call last)
Input In [4], in <cell line: 1>()
----> 1 cl.debug_bridge_0.start_xvc_server()

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/, in Overlay.__getattr__(self, key)
    358 """Overload of __getattr__ to return a driver for an IP or
    359 hierarchy. Throws an `RuntimeError` if the overlay is not loaded.
    361 """
    362 if self.is_loaded():
--> 363     return getattr(self._ip_map, key)
    364 else:
    365     raise RuntimeError("Overlay not currently loaded")

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/, in _IPMap.__getattr__(self, key)
    902 ipdescription = self._description["ip"][key]
    903 try:
--> 904     driver = ipdescription["driver"](ipdescription)
    905 except UnsupportedConfiguration as e:
    906     warnings.warn(
    907         "Configuration if IP {} not supported: {}".format(key, str(e.args)),
    908         UserWarning,
    909     )

File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/lib/, in DebugBridge.__init__(self, description)
    203 """Create an instance of the Debug Bridge Driver.
    204 Parameters
    205 ----------
    206 description : dict
    207     The entry in the IP dict describing the DMA engine
    208 """
    209 if type(description) is not ReprDict:
--> 210     raise RuntimeError('Description is not valid', str(description))
    212 # Insert register dict as they are not provided in the IP descriptor
    213 dbridge_registers = {
    214 'LENGTH': {
    215     'access': 'read-write',
    290 }
    291 }

RuntimeError: ('Description is not valid', "{'type': '', 'mem_id': 'S_AXI', 'memtype': 'REGISTER', 'gpio': {}, 'interrupts': {}, 'parameters': {'C_DEBUG_MODE': '2', 'C_NUM_BS_MASTER': '1', 'C_BSCAN_MUX': '1', 'C_EN_BSCANID_VEC': 'false', 'C_USE_EXT_BSCAN': 'true', 'C_USE_STARTUP_CLK': 'false', 'C_ENABLE_CLK_DIVIDER': 'false', 'C_TWO_PRIM_MODE': 'false', 'C_USER_SCAN_CHAIN': '1', 'C_CORE_TYPE': '1', 'C_EN_INT_SIM': '1', 'C_DCLK_HAS_RESET': '0', 'C_USE_BUFR': '0', 'C_XSDB_NUM_SLAVES': '0', 'C_CORE_MINOR_ALPHA_VER': '97', 'C_CORE_MINOR_VER': '0', 'C_CORE_MAJOR_VER': '1', 'C_BUILD_REVISION': '0', 'C_MINOR_VERSION': '1', 'C_MAJOR_VERSION': '14', 'C_FIFO_STYLE': 'SUBCORE', 'C_DESIGN_TYPE': '0', 'C_MASTER_INTF_TYPE': '1', 'C_EN_PASSTHROUGH': '0', 'C_XVC_HW_ID': '0x0001', 'C_XVC_SW_ID': '0x0001', 'C_PCIE_EXT_CFG_BASE_ADDR': '0x400', 'C_PCIE_EXT_CFG_VSEC_REV_ID': '0x0', 'C_PCIE_EXT_CFG_VSEC_LENGTH': '0x020', 'C_PCIE_EXT_CFG_NEXT_PTR': '0x000', 'C_PCIE_EXT_CFG_VSEC_ID': '0x0008', 'Component_Name': 'camera_link_pynq_debug_bridge_0_0', 'C_CLK_INPUT_FREQ_HZ': '300000000', 'C_S_AXI_DATA_WIDTH': '32', 'C_S_AXI_ADDR_WIDTH': '5', 'C_TCK_CLOCK_RATIO': '8', 'C_USE_SOFTBSCAN': '1', 'C_DEVICE_FAMILY': '0', 'C_IR_WIDTH': '0', 'C_CHIP_ID': '0', 'C_IR_ID_INSTR': '0', 'C_IR_USER1_INSTR': '0', 'EDK_IPTYPE': 'PERIPHERAL', 'C_BASEADDR': '0xA0020000', 'C_HIGHADDR': '0xA002FFFF', 'DATA_WIDTH': '32', 'PROTOCOL': 'AXI4LITE', 'FREQ_HZ': '100000000', 'ID_WIDTH': '0', 'ADDR_WIDTH': '16', 'AWUSER_WIDTH': '0', 'ARUSER_WIDTH': '0', 'WUSER_WIDTH': '0', 'RUSER_WIDTH': '0', 'BUSER_WIDTH': '0', 'READ_WRITE_MODE': 'READ_WRITE', 'HAS_BURST': '0', 'HAS_LOCK': '0', 'HAS_PROT': '1', 'HAS_CACHE': '0', 'HAS_QOS': '0', 'HAS_REGION': '0', 'HAS_WSTRB': '1', 'HAS_BRESP': '1', 'HAS_RRESP': '1', 'SUPPORTS_NARROW_BURST': '0', 'NUM_READ_OUTSTANDING': '1', 'NUM_WRITE_OUTSTANDING': '1', 'MAX_BURST_LENGTH': '1', 'PHASE': '0.0', 'CLK_DOMAIN': 'camera_link_pynq_zynq_ultra_ps_e_0_0_pl_clk0', 'NUM_READ_THREADS': '1', 'NUM_WRITE_THREADS': '1', 'RUSER_BITS_PER_BYTE': '0', 'WUSER_BITS_PER_BYTE': '0', 'INSERT_VIP': '0', 'ASSOCIATED_BUSIF': 'S_AXI'}, 'registers': {}, 'driver': <class 'pynq.lib.debugbridge.DebugBridge'>, 'device': <pynq.pl_server.embedded_device.EmbeddedDevice object at 0xffff871b0a30>, 'state': None, 'bdtype': None, 'phys_addr': 2684485632, 'addr_range': 65536, 'fullpath': 'debug_bridge_0'}")

I’m not sure what I’m missing here.

Thanks in advance for your help.



Hi @jacopoabramo,

This Python utility was added by a community member, so I am not hugely familiar with it.

I would suggest to use the traditional flow with the JTAG cable (micro USB). You only need to add the ILA in your design.

What OS are you using for development? If Linux, make sure you have installed the Vivado cable drivers.


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Hi @marioruiz , thanks for the reply.

I’m currently using Ubuntu in Windows Subsystem Linux (WSL). Should I download the drivers from the AMD website?


EDIT: nevermind, I just found the information here

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Just for an extra information for those who wish to use Vivado in WSL and want to attach a PYNQ board via USB to debug: you should install usbipd and follow the instructions on how to attach an USB port to WSL. You should carefully read the installation guide depending on wether you’re using Windows 11 or 10 as for the first support is guaranteed, while for the latter depends on the WSL kernel version you’re currently running and an update may be necessary.

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I was able to work around the “Description is not valid” error, see DebugBridge fails to connect · Issue #1429 · Xilinx/PYNQ · GitHub

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