ZCU111 DAC ADC Loopback keep getting stuck

Support
1

PYNQ Version : 3.0.1

Vivado version 2022.1

I am trying to build a simple ADC and DAC loopback setup for ZCU111 and getting stuck in the dac configuration step.

import numpy as np
import scipy
import scipy.io
import scipy.signal
import matplotlib.pyplot as plt

from scipy.signal import welch

import os
os.environ['BOARD'] = 'ZCU111'          

import pynq
from pynq import allocate
from pynq import Overlay

import xrfclk
import xrfdc

from time import sleep

SAMPLING_RATE = 4096  # MHz

INTERPOLATION_FACTOR = 8   
DECIMATION_FACTOR = 8      

CARRIER_FREQUENCY = 300  # MHz

NYQUIST_ZONE = 1

base = Overlay('sin_loopback/loopback_sin_zcubit')
rfdc = base.usp_rf_data_converter_0

def init_rf_clks(lmk_freq=122.88, lmx_freq=409.6):   # was 245.76 / 491.52
    xrfclk.set_ref_clks(lmk_freq=lmk_freq, lmx_freq=lmx_freq)

init_rf_clks()

dac_tile = rfdc.dac_tiles[0]                        
dac_tile.DynamicPLLConfig(1, 409.6, 4096)   <---- Get stuck here         
dac_block = dac_tile.blocks[0]
dac_block.NyquistZone = NYQUIST_ZONE
dac_block.MixerSettings['Freq'] = CARRIER_FREQUENCY
dac_block.UpdateEvent(xrfdc.EVENT_MIXER)
dac_tile.SetupFIFO(True)
dac_tile.StartUp()

My block design:

image
image1889×863 87 KB

ADC and DAC Settings (ADC tile 226 and DAC tile 228):

ADC
Digital Output Data = I/Q
Decimation = 8x
SPC = 2
Required Clock = 256 MHz
Mixer = Fine, Real → I/Q

DAC
Analog Output Data = Real
Interpolation = 8x
SPC = 4
Required Clock = 256 MHz
Mixer = Fine, I/Q → Real

System clocking:

ADC 226
Sampling Rate = 4.096 GSPS
Max Fs = 4.096 GSPS
PLL = Check
Reference Clock = 409.600 MHz
PLL Ref Clock = 409.6 MHz
Fabric Clock = 256 MHz
Clock Out = 256 MHz

ADC 226
Sampling Rate = 4.096 GSPS
Max Fs = 4.096 GSPS
PLL = Check
Reference Clock = 409.600 MHz
PLL Ref Clock = 409.6 MHz
Fabric Clock = 256 MHz
Clock Out = 256 MHz

And also the SPI ports are enabled; I have checked them.

One thing to note is my DS45 LED light is not on, which should be ON. I checked the jumper J110 that is there, which is required, but it still doesn’t work. Although I do not get any error for setting the PLL clock as stated above in the code.

Any help would mean a lot; I have been stuck here for days.

2

This is almost certainly a clocking issue. Are you sure you have the correct clock file for the LMX clock that uses a frequency of 409.6 MHz with an input clock of 122.88 MHz from the LMK?

Where did you get the 409.6 MHz clock file from?

3

I didn’t check that. I thought this came with xrfclk, and it didn’t even give an error while setting it to 409.6 MHz. Otherwise, if we set an unavailable frequency, it will throw an error.

4

Can you build the design using the default 122.88 MHz LMK and 491.52 MHz LMX clock frequencies?