I have set up Pynq with help of this documentation: Yet another EBAZ4205 writeup<br/>#3: PYNQ!
Pynq boots up and I get network communication. I was going through the steps of the Overlay Tutorial. After loading the overlay, the network communication is lost.
The ENET0 is connected via EMIO. So it has to be routed through the PL. The clock for the Ethernet phy is generated by the PS and routed to a PL pin.
As far as I understand the overlays, the overlay will replace the FPGA configuration, which is loaded at system bootup. So I extended the base design and added the “Add” IP block:
After loading the overlay, the ethernet stops working. This might be due to interruption of the phy clock and the connection between ENET0 and the phy.
- Am I right, that all needed FPGA block need to be reimplemented in the overlay? Or is there a possibility to partially reconfigure the FPGA. So the connection and clock to the ethernet phy is not interrupted?
- Is there a possibility to reinitialize the ethernet phy in linux during runtime (as a fall back solution)?