Accesing RAM from PL only

[cathalmccabe]

Hi,
If you are using a PYNQ-Z2 I presume you want to use the PS DRAM. You don’t need MIG, the memory controller is in the PS. You can access the PS DRAM fromo the AXI HP port.

You mentioned you don’t want to use the PS at all during running. From the PS, you will need to allocate some DRAM for your IP initially.

For the application that the FPGA will be used in later, any use of the PS should be avoided if possible for reliability reasons

You are using the PS RAM, but you don’t need the processor to do anything which I think is OK for your use case.

You can find some tutorials I made here:

GitHub - cathalmccabe/PYNQ_tutorials

This one may be useful, using a HLS AXI Master:

Tutorial: AXI Master interfaces with HLS IP

PYNQ HLS AXI Master tutorial Introduction Previous tutorials show how to build IP with AXI stream interfaces and how they can be connected in a Vivado project to an AXI DMA. The DMA can be controlled from PYNQ to send data to the IP and receive results. AXI stream interfaces are useful if you are connecting multiple IP together in a dataflow type architecture. However, you don’t have to use AXI streams and DMAs with HLS IP. HLS supports AXI master interfaces which can read and write data as r…

You can connect the AXI master to the HP port to access PS RAM.

You can also use a DMA (see other tutorials), and you can also do similar with HDL.

Cathal