Adding IP to a PYNQ overlay - tutorial problem

I have a Pynq-Z2 board and it is running Pynq 2.5. I have downloaded Vivado 2019.2 onto a windows machine running 8.1 pro and tried to rebuild the overlay according to Tutorial: Rebuilding the PYNQ base overlay but this fails when running source ./base.tcl with numerous errors such as:

CRITICAL WARNING: [BD 41-1377] Network address <0x4000_0000 [ 4K ]> is occupied by different slave segments, </btns_gpio/S_AXI/Reg> in </iop_arduino/mb/Data> and by </iop_arduino/mb_bram_ctrl/S_AXI/Mem0> in </ps7_0/Data>. This is illegal and must be resolved before passing validation
CRITICAL WARNING: [BD 41-1417] /iop_arduino/mb/Data/SEG_btns_gpio_Reg mapped into /iop_arduino/mb/Data at 0x4000_0000 [ 64K ] overlaps with the contiguous assignment of paired slave segments at 0x4000_0000 [ 4K ]
CRITICAL WARNING: [BD 41-1359] Failed to assign group of peripherals <
/iop_arduino/mb/Data [/iop_arduino/lmb/lmb_bram_if_cntlr/SLMB1/Mem]
/iop_arduino/mb/Instruction [/iop_arduino/lmb/lmb_bram_if_cntlr/SLMB/Mem]>.

Any help you can provide would be appreciated,


Tony Smith.

PYNQ v2.5 has only been tested with 2019.1. It looks like some updates are required in 2019.2

Can you install 2019.1, or do you have access to it?

I also wanted to check what you are trying to do? Rebuilding the base design isn’t essential.


I do not have access to 2019.1, it was a 4 hour download and install of 2019.2 so I am loathe to try and find 2019.1 and lose my 2019.2 setup as this is the Xilinx default download.
I want to modify the IP on the Z2 and saw this as the best way to start with a known bit file.


Tony Smith.