Adding MMIO to HDL Design Block

Hey all,

I implemented a calculator using VHDL, and have three 32b registers I use, two of which are inputs, and the third is an output. I’d like to interface with this using MMIO, but am not entirely sure where to start. I know that I can use the AXI Slave GP ports in order to use MMIO, but I’m not sure how to connect that port to the three registers. Any help would be appreciated.

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Hi @rngsys_a,

If you do not want to change your code, you can use AXI GPIO, you will need two of them. You can connect your inputs/output to the AXI GPIO and write/read from them.

An alternative is to use AXI4-Lite to communicate your calculator with the PS. If you Google for “AXI4 Lite peripheral in Vivado”, you will find plenty of resources to help you with this.


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I’ve gone the custom peripheral route and also used AXI GPIO. Output or input only GPIO are probably easiest.

If things get a little complicated or there are lots of single signals, I use AirHDL to build a register peripheral and then put the RTL module in the block diagram (use the .vhdl file). It’s also fairly easy to instantiate it inside whatever needs a register space.

Creating a custom AXI4 peripheral with Vivado seems to distract me from my actual task.

It is possible to update the Xilinx hardware description from the AirHDL json based register definition and get a working Pynq RegisterMap.

The free plan at would be sufficient for connecting a 3 register calculator. The strobes available when reading/writing are also handy for triggering logic on writes.

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Hi @jobrien,

I’m not familiar with AirHDL, it looks interesting. I saw that they are able to export an IP-XACT file. You might be able to use this file in Vivado to import the generate core into the IP catalog. However, looking at the website, I think you might need the professional for this. Were you using this flow to generate IP-cores or were you taking the generated RTL and wrapping it up for Vivado yourself?

All the best,

I’m lazy when it comes to packaging IP for something like what the OP was asking, so I include the couple VHDL files in my project and then in the BD do a right click “Add Module…”. It’s really quite painless since Vivado handles the wrapping in the background and gets all the interfaces right in this case.

If going the IP packager route I usually instantiate inside some RTL so I can avoid connecting lots of wires in the BD.

You need to use the VHDL files if you are following the “add module” path since you cannot add a SystemVerilog module directly to a BD.

Also, reduce the AXI_ADDR_WIDTH parameter down to something reasonable based on how much space you want the peripheral to take up in your address map.

I never tried anything with the IP-XACT files.

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The AXI GPIO was how I eventually solved my problem. Apologies for the delay, but for anyone else who might need to interface with a relatively small peripheral, this was an effective solution.