I recently changed the verbose version of an AXI4Lite interface (every port declared, etc.) into one based on records and local package-defined data types. For those who may be familiar – it’s the RDL framework developed by the folks at DESY in Hamburg.
The addresses are assigned, everything builds. The block design and bitstream all import successfully to PYNQ. However, when I try to access this interface, no errors show up; the whole PYNQ system crashes and I have to power cycle the eval board I’m working on.
Any ideas where I can start looking to troubleshoot this? I don’t even know where to begin.
delay_ctrl_top_0 suppose to use 4GB of memory?
Also, there is no need to manually create the MMIO object, the IPs are automatically assigned an MMIO object.
No it only needs to be like 16 bytes; 4 32-bit registers used to control the custom IP I’ve written, but there’s nothing else using the address space, and I assume vivado doesn’t route anything that isn’t tied to anything in synthesis. I manually create the MMIO object so I can just work with the address offsets.
The MMIO invokes a
mmap under the hood, so not sure if allocating 4 GB can have an impact.
Can you break down the cell where you do the MMIOs and use a smaller aperture to see which call is causing the crash?
The crash can cause because a read/write from thre AXI4-Lite time out or returned and error.
The cell where the crash happens is the simple
delay_mmio.write(0x8, 1), as seen in the screenshot I posted with the original question.
I suppose the same happens if you try:
You may need to add an ILA to this AXI4-Lite interface and see the behavior of the response channel.
Ok, I’ll try that and report back. Will take some time to synth
Yep, so it turns out this System RDL-based interface generator doesn’t raise BVALID, so the processor subsystem crashes waiting for it. Is there an option in the MMIO library to not wait for BRESP? I don’t have access to the repository guts where these AXI signals are handled.
Well, I’ve found where the problem is, but I have no clue why the problem is.
I returned to my verbose AXI Lite interface and for some reason the exact same problem exists.
The images here show an ILA wired to the AXI port in question, and show how completely contradictory the two are. I can’t see any break in the chain; everything gets passed along correctly except for the
BVALID signal, which is assigned correctly all the way up to the
.bd file where it’s passed along with the rest of the AXI signals. The other AXI interfaces, coded nearly identically (with the only differences being the user-defined registers) work just fine.
Have you come across a problem like this before? I’m pretty stumped.
axi_bvalid being driven in any other statement by any chance?
Does this happens if you try to write to a different offset?