Is there any documentation for providing HWH information for modules designed in HDL? My HLS modules have nice, named ports available from ip.register_map, but my HDL module (AXI slave) does not. In fact, when I try to access the register_map of the HDL module, it tells me that I need a HWH file. I do have that for the board-level design, but I suspect I am missing details for my HDL module.
FWIW, I can control the module by writing to the port addresses directly.
Is there any documentation available for creating my own HWH file when packaging an IP?
The process I went through for this design is to create a new project in Vivado, “Create & Package New IP|Create a new AXI4 Peripheral” and created my module in Verilog, integrated it with the AXI4 wrapper and packaged it. I then closed that project and created a new project, block design, with the Zynq subsystem and my IP package.
I’ve looked around for documentation on how to do this and have come up empty so far.