HWH for HDL (Verilog) AXI Module

Is there any documentation for providing HWH information for modules designed in HDL? My HLS modules have nice, named ports available from ip.register_map, but my HDL module (AXI slave) does not. In fact, when I try to access the register_map of the HDL module, it tells me that I need a HWH file. I do have that for the board-level design, but I suspect I am missing details for my HDL module.

FWIW, I can control the module by writing to the port addresses directly.

Is there any documentation available for creating my own HWH file when packaging an IP?

The process I went through for this design is to create a new project in Vivado, “Create & Package New IP|Create a new AXI4 Peripheral” and created my module in Verilog, integrated it with the AXI4 wrapper and packaged it. I then closed that project and created a new project, block design, with the Zynq subsystem and my IP package.

I’ve looked around for documentation on how to do this and have come up empty so far.

If you are using the packaging wizard you can add registers on “Addressing and Memory” page. If you right click on the address block you are using for the AXI-Lite interface you can “Add Register” which will create a new sub-pane where you can edit the details of the registers you add.

If you are packaging using TCL directly the same can be accomplished with the ipx::add_register TCL command. This will create a new object you can set_property on to configure it the same as any other Vivado TCL object.

One thing to note is that they way PYNQ interprets this data is that the “Name” is what gets propagated as the name of the register and the “Description” appears in the Python docstring. The “Display Name” is unused.


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Perfect. Thank you. That worked.