Any "low-level" AXI4-Lite read/write method (e.g. manipulating ARADDR/AWADDR) in PYNQ?

PYNQ version & Board name & Tool Version:

  • PYNQ: latest (3.0)
  • Board name: pynq-z2 (xc7z020clg400-1)
  • Tool version: Xilinx Vivado 2023.1

My design consists of a custom IP, with an AXI4-Lite compatible interface. I followed the tutorial and Vivado automatically connected the IP to the M_AXI_GP0 of PS.

However, the IP directly takes the AWADDR/ARADDR as the control word or opcode. In order to control the IP, I need to use something like device.write(addr, data) or,while the pynq.axigpio does not support read/write with an address. So my question is:

  1. Does Pynq provide some kind of “low-level” API to manipulate the port-level signal for the interface over M_AXI_GP0?
  2. Do other AXI ports support reading/writing with address, and how should I switch them?

Thank you so much!

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Hi @marvtao,

Welcome to the PYNQ community.

Check out the MMIO driver.

Here is an example:

In genera, every AXI4-Lite IP in your design is assigned a MMIO driver by default.

So, you can do .read(addr) and .write(addr, value)



Thank you so much Mario!

MMIO looks promising, but it requires the address must be the multiple of 4. I understand that MMIO is designed to align by word rather than by byte. But, are there any really fine grained low level APIs for manipulating such as AWVALID/AWADDR/WDATA ports?

If no so, I have to modify the RTL to make the opcode multiple of 4, and do everything all over again😗

Hi @marvtao,

There’s no finer granularity as the the M_AXI_GP0 is 32-bit wide.


Thank you for this precious information. Now I’m much assured about what I’m going to do next.


1 Like