I am trying to configure a timer in a custom overlay for use in Pynq.
In Vivado, I have built an overlay which instantiates a range of IP. This includes two AXI BRAM Controllers (via Block Memory Generators), two AXI UART16550, an AXI GPIO, and an AXI Timer.

With exception to the timer, everything works correctly. I access the GPIO through the Pynq GPIO library. The UARTs and BRAMs, I access directly with MMIO. I think i’ve got a decent handle on how to use these.

I’ve attached my memory configuration settings below.

I am attempting to configure the timer, following the documentation:

I have attached my notebook.

However, when trying to execute an MMIO read or write call in the memory space, the Kernel “appears to have died”. I’ve tried all sorts of different things, but simply cannot get any calls to MMIO in this space work.

I am using pynq-2.6.0, on a Pynq-Z2 board. On the PS UART, I see some information when this occurs:

unhandled fault: external abort on non-linefetch (0x818) at 0xb6f42004 pgd = b09b81cb [b6f42004] *pgd=16fcc831, *pte=41400743, *ppte=41400c33

What am I missing here?

Unfortunately, as a new user to the forum, I can’t seem to upload my .hwh or other files… I appreciate it’s an anti-spam feature, but it’s prohibitive to me providing the necessary information here…


timer_test.ipynb (2.1 KB)

Hopefully you should be able to upload the hwh and bit files now. Let me know if you’re still running into issues there.

Your notebook mentions enabling interrupts - is the timer connected to the PS interrupt line?

You’re doing three writes to the MMIO device, do you know which of the three is causing the issue?


Hi Peter, thanks for having a look at this.

To investigate, I implemented the same functionality in C in Vitis, and found the same issue occurring - which brought me to the conclusion there must still be some hardware issue.

Having a more careful look at the Vivado block design, I found that the AXI interface for this Timer wasn’t connected correctly to the PS. I had used the automation assistant to perform this function, and it had mapped it up to an AXI Interconnect - but the fifth port didn’t appear to be actually connected to anything inside the IP.

I suspect user error somewhere along the way…

I replaced this with an AXI SmartConnect, which brought the system to life in both Vitis C and Pynq.