Hi guys,
In the pre-baked base overlay, the SPI frequency seems to be set a 6.25MHz (1/16 divider off the 100MHz CLK). In the python environment, can we manipulate the SPI frequency without having to reconfigure the base overlay with vivado? For example, I will need to generate a 50MHz SCLK for the SPI interface…
Thanks!
The available IP doesn’t support run time clock configuration, otherwise support for this would be included.
The IP accepts an external clock that it then steps down internally. It may be possible to dynamically update the clock, but in the PYNQ base overlay, this clock is the main 100MHz clock used to clock most IP in the design, including the MicroBlaze processors. It probably isn’t a good idea to try and change this.
Cathal
From what I understand, the SPI controller is configured through a divider from the master clock (100MHz). It still would not be a good idea to change the divider ratio itself while keeping the master clock the same thus not impacting the microblaze timing?
The plan was to modify the clock divider setting in the AXI-SPI IP in the base overlay. I have not been able to test this since I have been running into a slew of problems trying to rebuild the base
TCL in Vivado.
Yes, it would not be a good idea to modify the main clock. This may be a very quick way to check if you wanted to test your design at a slower clock speed.
It would be much better to modify the clock divider.
What problems are you having with rebuilding the design?
Cathal
I keep running into “can’t unset ‘period’: no such variable” error
EDIT: This was resolved by putting my glasses on and reading that Glasgow release (PYNQ 2.5) is designed for Vivado 2019.1 release which is what I am working with. Everything runs smoothly now.
I was able to modify the clock divider and rebuild the base overlay.
(I set the divider to 16 with a multiplier of 4, because I need a slower speed for my application)
Although, now I am having the problem of microblaze timing being impacted.
When calling SPI transfer function, the SS is not idled low for enough time, i.e. the SS goes high again before all the clock cycles have finished.
What is the correct approach to edit/compile the spi.c code found in the sw_repo folder?
(Im assuming this is not done during the bitstream generation)
Must I use the SDK to compile? If so, how do I get it to work on the Pynq-Z1 board?
Are there any good examples to follow for this?
The easiest way is to edit the files in a copy of the PYNQ repository on a Linux machine with SDK and a reasonably current version of Anaconda installed and then run python3 setup.py sdist to create a new pynq-2.6.0.tar.gz which you can copy on to the board and then run sudo pip3 install pynq-2.6.0.tar.gz to install your new version on the board. After running sdist you can also copy the appropriate libxil.a files manually but I find it easy to get confused when doing that.
Peter
I was able to rebuild the board support package using the instructions on page 119 of Pynq Documentation, (excluding step 4). I just have to make a copy of the repository folder every time I run make, because of some error saying the hw project exists already. I then just replace the bsp_iop_pmod folder with the one generated, renaming it to the same name, removing extra directories, and making all sub-files executable. This works for me since I am only making use of the pmod bsp.
Thanks,
Rey