Incorrect PL Clocks on PYNQ-ZU board from TUL

Support
1

Hello,

I have noticed that on the PYNQ-ZU board, the clock frequency of the PL cannot be set to 100 MHz from pynq, instead it is set to 98.88 MHz. You can see the output after loading an overlay.

Why is it so? Inside the Vivado block diagram, the PL frequency is set to 100 MHz

image

2

Check the clock settings in Vivado.
When you try to set a clock in PYNQ, it will set it to the nearest achievable frequency.

Cathal

3

Hi, As Cathal suggested, double check the PL clock settings in Vivado, there are fields for requested and actual. Most likely you will see that the actual matches what PYNQ is showing. The PS PLLs that are used for these PL clocks are good PLLs but are simpler PLLs that have a finite list of rational clock multipliers. The distribution to the PL logic is also not as good as other clocking options.

Also, do be careful if changing the PS PL clocks on the fly at run time. When Vivado creates a bitstream it uses the known clock settings to ensure the design meets its timing requirements. If you change clocks that are driving logic while the bitstream is running, Vivado will not have run timing analysis against the new clock speeds. In some cases, it is safer to tell Vivado you are using a faster clock and then slow the clock down later than it is vs speeding up later. That said, changing the settings of the PLL can also change the clock’s jitter which could also cause issues with meeting timing in some designs. There also may be issues with glitches or short pulse widths while changing the PL rates and the logic should be properly reset afterwards to make sure it is in a known state. There are designs you can get away with changing the clock on the fly and there are designs that you cannot, which is which is not a secret being held back. Rather, it is not well defined because it depends on how Vivado itself ends up place and routing the design. The safest and proper practice is to tell Vivado the clock’s rate and always use the clock rate you told it.

There are better PLLs and clock generators in the MPSoC part, look into the Clocking Wizard IP for Ultrascale+ which can achieve closer to the desired clock values and have other benefits. One tradeoff is there isn’t a built-in Python object to read back settings or change it from the PS.

Kind regards

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