I have been at this for a few days now with no luck. I have been attempting to rebuild the base overlay in vivado so that I can edit the AXI SPI1 clock divider attached to the Arduino IOP (I could not set it properly with XSpi in cell magic via python). Once I source the IP and build (all build correctly), I can easily navigate to the SPI1 and change the divider.
I save the project, generate the HDL wrapper, and then run synthesis which runs fine. Implementation, on about 4 machines now (all done with fresh pulls from the 2.5 release) give me the following error: