Base Overlay Generate Bitstream Fail - PYNQ 2.5 - Vivado 2019.1

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Hi guys,
I have been at this for a few days now with no luck. I have been attempting to rebuild the base overlay in vivado so that I can edit the AXI SPI1 clock divider attached to the Arduino IOP (I could not set it properly with XSpi in cell magic via python). Once I source the IP and build (all build correctly), I can easily navigate to the SPI1 and change the divider.

I save the project, generate the HDL wrapper, and then run synthesis which runs fine. Implementation, on about 4 machines now (all done with fresh pulls from the 2.5 release) give me the following error:

error_1
error_13822×1865 236 KB
error_2
error_23008×1840 116 KB
error_3
error_32923×1829 147 KB
error_4
error_42835×1452 170 KB
errpr_3
errpr_31148×1834 102 KB

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SOLVED: The base.xdc file was not loaded correctly.

Forgive me for all of my trivial posts. I am a novice at FPGA design + Vivado tools. I hope that others who are exploring this hardware can learn from my mistakes.

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