AXI DMA issue when trying out without loopback in RFSoC2x2

I was trying a project which is quite similar to strath-sdr/rfsoc_ofdm: PYNQ example of an OFDM Transmitter and Receiver on RFSoC. ( My project is at the below location -
himanshudutta11/rfsoc_nrssb (
The issue is that whenever I am trying to receive the samples through AXI stream from RFADC, (there is a wideband antenna connected to RFADC [have not connected an LNA and LPF yet, but I can connect them as a next step]), somehow it is stuck after the first axi transfer.
First transfer->
Second transfer →

Even OFDM modem as mentioned above get stuck in the inspector.get_frame() if I run without loopback.

def get_frame(self):
    """Get a single buffer of time data from the logic fabric
    self.data_inspector_module.reset = 0
    self.data_inspector_module.enable = 1
    self.axi_dma.recvchannel.wait() --> stuck here

What is the size of the buffer you want to transmit? This delay issue can occur when the size of the lower or higher than a DMA size requirement.

Is it about the axi_dma.buffer_max_size?

Initially I didn’t set this explicitly and the default value what I observe was 67108863 = 0x03FFFFFF, I tried to modify it to 256, 512, 1024, it is still stuck.

The AXI_DMA structure looks like below:

What is inside the nrssb.inspector.buffer? Can you increase the number of element in that buffer?