Hi there, I am trying to run a toy example for AXI DMA on PYNQ-Z1. I use a simple AXI4-Stream DATA FIFO with the DMA, so that I receive in the PS what I send. I tried 4 different topologies, and none of them worked for me: In the first trial ( 1.pdf (62.5 KB) ), I used the simple DMA mode (Dire…

Looks like you edited your post since I replied. You have only connected the stream side of your IP in the diagram in 1.pdf to the FIFO. There is no connection to DRAM. Your code tells the DMA to read data from the “input_buffer”, located in PS DRAM, and write it to the DMA stream interface M_AXIS…

Did you try the example here: https://github.com/Xilinx/PYNQ_Workshop/tree/master/Session_4 6_pynqtutorial_dma Cathal

Yes I tried that (as you can see in my main post above), but it didn’t work for me.

Hi, ( you’re right, I posted by mistake before the post was complete :slight_smile: ) Okay that was something the automatic connection did without a notice, but in the other trials (2,3,4) the DMA was correctly connected to the DRAM but didn’t work neither. However, I tried to reconnect the first…

Scatter gather is not currently supported. Cathal

But for some reason this is not mentioned here: https://pynq.readthedocs.io/en/v2.5/pynq_libraries/dma.html it only says (The DMA class supports simple mode only) and it’s not really clear that this is referring to Direct Register Mode. I would suggest to clearly state that Scatter/Gather is not c…

As a summary, here are my trials: [DMA_Trials] The corresponding designs can be found here: 1.pdf (62.5 KB) 1_modified.pdf (69.0 KB) 2.pdf (70.4 KB) 3.pdf (98.5 KB) 4.pdf (78.5 KB) 5.pdf (71.7 KB) 6.pdf (77.1 KB) Here are my notes: 1- Don’t use Scatter/Gather. 2- If you want to use interrupt,…

Hi again, In DMA documentation it’s mentioned that TLAST signal must be set in order for the transaction to complete the transaction. If I want to use my own IP (generated by Vivado HLS), how to set the AXIS signals (TLAST, TUSER, TID, TKEEP, TSTRB, TDEST) ? I guess when I send the last data chun…

[image] rashedkoutayni: If I want to use my own IP (generated by Vivado HLS), how to set the AXIS signals (TLAST, TUSER, TID, TKEEP, TSTRB, TDEST) ? I guess when I send the last data chunk in the stream, I have to set TLAST to 1, otherwise 0. Is that correct ? Yes. If using HLS, for most IP…

Hi Cathal, thank you for you answer. What I meant is that I don’t necessarily write an output for each input, I might only write an output for every set of inputs. In this case: I don’t know how to pass the the signals from input to output (especially that I have more than a sub-function in the…

You can write values to these signals inside conditions in your HLS code. e.g. if (i==16){ last = 1; }else{ last = 0; } USER is a user defined signal, so you don’t need to set it to anything. If your IP doesn’t use it, and you know any downstream IP doesn’t use it, then you can ignore it. O…

AXI DMA not working on PYNQ-Z1

Support

Topic		Replies	Views
Axi-s dma pl->ps Support	8	5090	February 13, 2023
FIFO using PYNQ DMA Support	7	5000	July 10, 2020
Tutorial: PYNQ DMA (Part 1: Hardware design) Learn	30	40716	October 11, 2025
AXI DMA puzzle (maybe) Support	11	384	August 15, 2025
Tutorial: PYNQ DMA (Part 2: Using the DMA from PYNQ) Learn	4	20859	January 10, 2023

AXI DMA not working on PYNQ-Z1

Related topics