PYNQ: PYTHON PRODUCTIVITY

Axi_dma reset behaviour

Hi,

I am testing some DMA designs and have run into some perplexing reset behavior. I suspect it is more related to the IP itself rather than PYNQ. The relevant part of the BD is

axis_counter counts to some value asserting last at that value, it asserts valid one clock after coming out of reset (peripheral_aresetn). The axi_dma reset is connected to interconnect_aresetn.

The issue is that axi_dma seems to expect 4 stream data beats after coming out of reset,

What is the dma IP expecting? The axi_dma registers are not changed by any of my test code, ext_reset_in to the reset IP is controlled through GPIO.

RegisterMap {
  MM2S_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic_BD_Enable=0, 
      IOC_IrqEn=0, Dly_IrqEn=0, Err_IrqEn=0, IRQThreshold=0, IRQDelay=0),
  MM2S_DMASR = Register(Halted=0, Idle=0, SGIncld=0, DMAIntErr=0, 
    DMASlvErr=0, DMADecErr=0, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC_Irq=0, 
    Dly_Irq=0, Err_Irq=0, IRQThresholdSts=0, IRQDelaySts=0),
MM2S_CURDESC = Register(Current_Descriptor_Pointer=0),
MM2S_CURDESC_MSB = Register(Current_Descriptor_Pointer=0),
MM2S_TAILDESC = Register(Tail_Descriptor_Pointer=0),
MM2S_TAILDESC_MSB = Register(Tail_Descriptor_Pointer=0),
MM2S_SA = Register(Source_Address=0),
MM2S_SA_MSB = Register(Source_Address=0),
MM2S_LENGTH = Register(Length=0),
SG_CTL = Register(SG_CACHE=0, SG_USER=0),
S2MM_DMACR = Register(RS=0, Reset=0, Keyhole=0, Cyclic_BD_Enable=0, IOC_IrqEn=0, 
Dly_IrqEn=0, Err_IrqEn=0, IRQThreshold=1, IRQDelay=0),
S2MM_DMASR = Register(Halted=1, Idle=0, SGIncld=0, DMAIntErr=0, DMASlvErr=0, 
DMADecErr=0, SGIntErr=0, SGSlvErr=0, SGDecErr=0, IOC_Irq=0, Dly_Irq=0, Err_Irq=0, 
  IRQThresholdSts=0, IRQDelaySts=0),
S2MM_CURDESC = Register(Current_Descriptor_Pointer=0),
S2MM_CURDESC_MSB = Register(Current_Descriptor_Pointer=0),
S2MM_TAILDESC = Register(Tail_Descriptor_Pointer=0),
S2MM_TAILDESC_MSB = Register(Tail_Descriptor_Pointer=0),
S2MM_DA = Register(Destination_Address=0),
S2MM_DA_MSB = Register(Destination_Address=0),
S2MM_LENGTH = Register(Length=0)
}

I doubt if Pynq is involved but I thought I should post here as well as the appropriate Xilinx community forum.

I think your design has some connection issues. See the connection here:

Usually the interconnect_aresetn should only go to the reset for AXI interconnect ARESETN, and peripheral_aresetn can go to IPs or other AXI interconnect slave/master resets.

Hi rock,

Thanks for the pointer, I see that the resets should be wired as you suggest.
It turned out that the reset wiring was not involved in the ready after reset behavior, this is due to the buffer in the DMA IP ( FWFT register slices etc). and the 4 beats after reset is documented. Originally the 4 data beats would not appear and the buffer would start at 4, but this was due to some other signaling issues the BD in this post now works as expected with PYNQ.