PYNQ: PYTHON PRODUCTIVITY

Having trouble sending data from/to DMA

Hi all,

Target Device: Pynq-Z2

I’m working on a controller that will complete image convolution on hardware. I feel like I am very close to successfully doing this but the DMA is giving me some annoying issues…

So for reference this is a screencap of my Vivado BD:

I’m using a an AXI slave port for setting filter values and control registers for things like image width/height etc. I am also using an AXIS slave-stream port to input pixel values via DMA and an AXIS master-stream port for my convolution values to output via DMA. The actual convolution happens on an external IP and this is what the other output signals go to.

I’ve written a test bench to load filter values/set control registers via the AXI slave port and then begin a data stream using AXIS port in Vivado. The simulation consistently works as expect even though I am loading random values. This is a screenshot of my test completing.

The issue is that when I run a jupyter python script, if I send more than one line of data I don’t seem to get any response from DMA and have to manually interrupt the kernel, if I send only one line the calculations in the output buffer are definitely incorrect.
At this point, I think the real issue lies with the way my logic receives the incoming values from DMA over AXIS. I’ve successfully implemented a very simple streaming device to invert pixel values sent from DMA and it also featured control registers so this is why I’m confused at my issue.

I’m not sure how helpful this is, but this is what my simulation waveform looks like when receiving data via AXIS. I’ve attached the controller’s verilog file if that helps but its a decent chunk of code to sort through.

AXI_Convolution_Controller.v (12.0 KB) (Controller)
PL_Convolution_Simple.ipynb (10.0 KB) (Jupyter Sketch)

Any help would be appreciated!

Did you write the logic for the AXI stream yourself? There is a wizard to generate the AXI stream logic in Vivado (in the IP Packaging Wizard). This would eliminate one possible source of possible problems.

Do you know you can put an ILA in your design? It might be worth doing this to check the inputs/outputs of your IP and the DMA.
I’d check what is happening with TLAST. This is a common source of issues with DMA.

You might also want to check the status of the DMA.

Cathal