PYNQ: PYTHON PRODUCTIVITY

Connect DMA to non power of 2 stream

I am developing a simple design to test the vivado fft block. I connect my fft directly to the DMA and I simply run some transformations of my signals. I have already tested my design in PYNQ and in works perfectly.

However I was trying to analyze how the input data width of my fft impacted the output resolution. I have been able to test my design for data widths that are padded to a power of 2 (as an example, 16bits input data width is padded to 32, 25bits input data width is padded to 64bits).

However if I select a data width equal to 17, my stream is padded to 48bits, and I am not able to connect it to my DMA.

How can I solve this problem? Is there a way to connect the 2 IPs?
Here is my design

You may be better asking this on the Xilinx forums as this is not a PYNQ question.
The S_AXIS_DATA port on the FFT block is a bundle of all the signals. You can’t expand it and partially connect some signals to the underlying signals. IPI uses an ‘all-or-nothing’ approach. You either connect the ports using the bundled interface, or you expand it and connect every signal individually.
You should be able to connect the IPs and Vivado will automatically remove redundant signals.
The DMA doesn’t support arbitrary widths, so there will be some slicing of signals in HW/padding of data in software.

Cathal

as a suggestion, you can use axi stream data width converter followed by axi4-stream subset converter in the middle of your IP and DMA.