Hi everyone, i am confused of how to make the A[2][2] and B[2][2] arrays as input and AB[2][2] as the return output in vivado hls?
Because i am not good at this kind of port, any advice will be helpful.
Also, I am trying to use axi ports so that i think it is easy to implement on ultra96 pynq board with python code.
Tim
Have you tried the matrix multiplication example when creating the project? There are some existing code there. Also tutorial can be found online: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug871-vivado-high-level-synthesis-tutorial.pdf