PYNQ: PYTHON PRODUCTIVITY

How to connect custom HLS IP to Zynq board

I’m new to PYNQ board, but my goal is very straightforward: do a matrix multiplication using the pynq board.

I have an IP created using HLS that looks like the following:

void matrixmul(
  mat_a_t a[MAT_A_ROWS][MAT_A_COLS],
  mat_b_t b[MAT_B_ROWS][MAT_B_COLS],
  result_t res[MAT_A_ROWS][MAT_B_COLS])
{
    #pragma HLS ARRAY_RESHAPE variable=b complete dim=1
    #pragma HLS ARRAY_RESHAPE variable=a complete dim=2
    #pragma HLS INTERFACE ap_fifo port=a
    #pragma HLS INTERFACE ap_fifo port=b
    #pragma HLS INTERFACE ap_fifo port=res
    mat_a_t a_row[MAT_A_ROWS];
    mat_b_t b_copy[MAT_B_ROWS][MAT_B_COLS];
    int tmp = 0;

    // Iterate over the rowa of the A matrix
    Row: for(int i = 0; i < MAT_A_ROWS; i++) {
        // Iterate over the columns of the B matrix
            Col: for(int j = 0; j < MAT_B_COLS; j++) {
            #pragma HLS PIPELINE rewind
            // Do the inner product of a row of A and col of B
            tmp=0;
        // Cache each row (so it's only read once per function)
       if (j == 0)
          Cache_Row: for(int k = 0; k < MAT_A_ROWS; k++)
              a_row[k] = a[i][k];
  
       // Cache all cols (so they are only read once per function)
       if (i == 0)
           Cache_Col: for(int k = 0; k < MAT_B_ROWS; k++)
               b_copy[k][j] = b[k][j];

      Product: for(int k = 0; k < MAT_B_ROWS; k++) {
        tmp += a_row[k] * b_copy[k][j];
      }
  res[i][j] = tmp;
}

}
}

And I import the design into Vivado, which that looks like this:

My question is, how do I go about connecting these 2 components? Any help would be appreciated, thank you.

@youn123 if you use axi instead of fifo interfaces it should be easier to connect to the PS.

#pragma HLS INTERFACE s_axilite port=return
#pragma HLS INTERFACE m_axi depth=<MatrixSize> port=a
#pragma HLS INTERFACE m_axi depth=<MatrixSize> port=b
#pragma HLS INTERFACE m_axi depth=<MatrixSize> port=res 

You have to replace with an appropriate valite. The first pragma creates an AXI4-Lite interface to control the module.

You also need to enable the HP ports of the PS.

After that you can Run Connection Automation twice and the block design should look like this

You can also use AXI4-Stream for a,b and res and use other way to move data.

Do you have any preference about how to communicate the IP with the PS?

Mario

1 Like

This example may also be of interest.

Cathal

1 Like