VIVADO block port design question

Fig. 0 is the A&B that we want to preset first.

  1. We use the “Directive” in the right column to automatically generate “pragma” for our inputs A and B (Fig.1), but we are not sure if this is correct, the following error occurs (Note 1).

2.There is an article above this time, a friend left a message asking me to connect the CLK (Fig.2), but a critical warning still appears (Fig.3). (Note 1), also without critical warning.

Note 1: ERROR! !>>>[BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_0/M_AXI_GP0_ACLK

fig.0

fig.1

fig.4

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You should change the INTERFACE to AXI STREAM (axis ) or AXI MASTER (M_AXI).
It looks like you changed it to M_AXI (AXI MASTER) in the last screenshot.

If you use AXI masters you can follow this post:
https://discuss.pynq.io/t/tutorial-axi-master-interfaces-with-hls-ip/4032/4

Cathal

PS
If you use AXI STREAM you need a DMA.
https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133/28
https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344/2

I’m sorry, I can find the following way of writing in the examples I used on the Internet
#pragma HLS INTERFACE s_axilite port=a
But in my rough understanding, this can only accept numbers, my main question is, I want the matrix to be the input, how should I write it? Sorry, I can’t find the answer from your teaching

You can’t (easily) use AXI lite. With AXI lite you have to write all the data you want to transfer to registers. Depending on the size of your array, you may reach a limit for the number or registers you can have. This is also slow and inefficient and should not be used for transferring arrays.
AXI lite is generally only used for reading/writing control and status data.

The easiest way to implement your design (in my opinion) is to change the a,b, and c ports to AXI STREAM, then add a DMA to manage the data transfer.

You can follow these two tutorials:
This only uses an input and output (a,b) so you need to a third AXI stream interface for “c” in your design.
https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344/2

https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133/28
Each DMA can have 1x input steam, 1x output stream, so you need 2 DMAs (one with 1 input stream and an output stream, and the other with 1x input stream.

Cathal

Thank you for your reply, we based on the teaching of your reply,

It is found that the “AXI4-Stream Data FIFO” link will conflict with the input and output interface we designed (sda), so we refer to another link

, there is no “AXI4-Stream Data FIFO” in this teaching, which can make “sda” connect to the input and output of DMA smoothly (Fig.1), but according to this teaching to the end we have the following two serious warnings (Fig.2).

After some searching we found that TLAST seems to be related to “hls::axis<float, 0, 0, 0>” according to this link
Vitis-HLS-Introductory-Examples/example_test.cpp at master · Xilinx/Vitis-HLS-Introductory-Examples · GitHub,
However, the programming language we wrote is C language, and I don’t know if it can match.


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You don’t need the AXI FIFO. This is used in the example to loopback from one DMA write channel → read channel.
You should replace this with your IP.

The source code for the example in the tutorial is here:
https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/blob/2021.2/Interface/Streaming/using_axi_stream_with_side_channel_data/example.cpp
Use this as a template for your application.
It shows how to manage TLAST. If you do not set TLAST it will be removed.

TDATA_NUM_BYTES does not match …

You have a data width mismatch between your IP and the DMA. It looks like you set the DMA width to 32 bits but the output from your IP is 16 bits. You can change the width of the DMA, or use an AXI interconnect to convert from 16-bit to 32-bit. Changing the width in the DMA is simpler.

You can find the settings for this in the “DMA read and write channels” in the DMA tutorial

Cathal

Regarding the issue of TLAST, we have tried to use your code, but it seems that the code is only applicable to .cpp files, but our design is .c files, and it seems that it cannot be written in c language.
Regarding the problem of data width mismatch, we have tried a lot of setting adjustments (Fig.1), but still can’t solve our problem, can you please clarify?

You can change the extension of the .c file to .cpp. This will use the C++ compiler, but you don’t need to change any other code. The C++ compiler supports C code.

For the width, change the Stream Data Width. (uncheck AUTO).

Cathal

According to the provided link teaching, the current pre-problem of the TLAST program is still stuck (Fig. 1), and three Errors are attached, hoping to help answer
Error: [HLS 207-3337] type ‘hls::stream<ap_axis<32, 2, 5, 6>>’ (aka 'stream<hls::axis<ap_int<32>, 2, 5, 6>> ’ ) does not provide a subscript operator (Fig. 2) (Fig. 3)

I’m really embarrassed to ask so much, but I really want to understand this,
I’m not quite sure why they don’t work, aren’t they simply “equals”?
In addition, what is the tmp of “ap_axis<32,2,5,6> tmp;” in the program? I look like it is our input data, how did it actually introduce it?

image_2022_09_15T08_20_31_956Z

error

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USe .read(0 and .write() methods. See the example code.

See reference here on streams:
https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Using-HLS-Streams

Cathal

But we have really tried many times about the writing method of read&write, but the Errors have not changed so far. Do you have more relevant information for reference? I have tried everything that I can find and it does not match us. Do you have more suggestions?

Our input is a 1x28 vector, and the output is a 4x4 matrix. Is there a way to pass it in smoothly? We have really tried many methods.

p.s. The program in the figure wants to split the input into two matrices [1x16] [1x12].
image_2022_09_15T16_23_08_419Z

Can you post your source code?

Cathal

I’m very grateful for your help, and I can’t thank you enough.
Here’s my source code.
sda.zip (4.8 KB)

I thought your design was a simple example, not 600+ lines :wink:

I’d suggest you try build a simple example to understand the interfaces, and then build up your design.

Your problem is that you have the stream, and then try to assign it to a float. You can’t automatically cast between these types. That is why this line failed, not because of the read():

A_tb[i]=input.read();

If you need floats in your calculations, you should use float as the input interface. If you change your function prototype your code should compile:

line17:
float sda(hls::stream< float > &input,
		  hls::stream< float > &output)

I’d encourage you to think about what this means.

If you use ap_axis<32, 2, 5, 6>, this is a 32-bit number with 2 integer bits. , and 30 fractional bits. If you then convert this number to a float, you will lose something in the conversion. If you then do your calculation, and take the result (float) and convert back to the fixed point, you will lose something again.

You probably have other issues with you code, but rather than debug this whole application (or optimize it for HLS) I suggest you start with a simple example, get the interfaces correct and make sure you understand them, and the add your code to the body of the example.

Cathal

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