I have a Vivado design with 2 HLS IP cores. The interface between them is AXI Stream. I would like to know what is the depth of the FIFO generated for that AXI Stream. For example, if the first IP core (the producer) write elements faster than the second IP core (the consumer) reads them, how it will work? How many elements could be waiting on the AXI Stream between them? Does the producer “waits” for the consumer to read the elements before producing new ones?