Hello everyone,
I have a Vivado design with 2 HLS IP cores. The interface between them is AXI Stream. I would like to know what is the depth of the FIFO generated for that AXI Stream. For example, if the first IP core (the producer) write elements faster than the second IP core (the consumer) reads them, how it will work? How many elements could be waiting on the AXI Stream between them? Does the producer “waits” for the consumer to read the elements before producing new ones?
This isn’t a PYNQ question. You should post any questions like this and any follow up on the Xilinx forums.
If you have separate HLS IP, no FIFOs are added to the AXI streams. In Vivado you could insert a FIFO if required.
The AXI protocol supports flow control so you are correct, the consumer IP will cause the producer IP to wait if it can’t keep up. Your problem will be if the source to the producer can’t wait. You may need to insert the FIFO there.
Cathal
Thank you @cathalmccabe
Now, I get the behavior of the AXI Stream between IP cores