PYNQ: PYTHON PRODUCTIVITY

AXI-Stream FIFO

PYNQ provides several methods to move data from PS-PL IP’s that are connected to AXI Streaming Master ports, e.g., DMA. However, if an AXI-Streaming FIFO needs to receive data directly from the PS via an AXI Interconnect (without a DMA in between), there are no methods available to do that, or at least I haven’t found it. Is this possible at all?

Hi @Rho81

You need a DMA to convert AXI to AXI-Stream. This is not a Pynq limitation, but how Vivado works with AXI protocols; they’re not interchangeable.

Thanks,
-Pat

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Hi patocarr,

Thank you for replying. Yes, there is that option by including the DMA.

On the other hand, what I think PYNQ should be helping to abstract is the programing sequence for the AXI FIFO, as described in the following document(page 36):

Is there a plan to include the AXI FIFO programability through PYNQ APIs?

Thank you.
Rho

@Rho81

That AXI-Stream FIFO is intended to be used mainly by the PL Ethernet core and its functionality is similar to the AXI-DMA IP Pynq already supports.

Thanks,
-Pat

I would say this is more a CPU limitation. The ARM reads/writes memory mapped devices. You need something to convert from MM to Stream. The DMA can do this.

A stream usually implies a “reasonable” amount of data needs to be transferred.

The AXI to FIFO would be connected via AXI lite. The CPU would spend a lot of time writing to it. i.e. CPU would write each data beat. I think performance would be relatively low, and you would be consuming a lot of CPU time. Depending on volume of data you need to transfer this may make sense for your application. i.e. if it is very small amounts of data. I would think DMA is much more likely to be applicable in the majority of cases.

If you are writing HLS you can also design your IP with an AXI master port, so it can access memory directly.

More info about your IP, or what you are trying to do would be helpful.

Regards,
Cathal