Best interface for passing value between IP cores

Hi everyone,

I have a design with two kernels made using Vitis HLS. The second design must start after the first one and use the result of the first one (single value). What would be the best interface to pass that argument and link them on Vivado? And how could I implement it in Vitis HLS?

At the moment I’ve tried to output in the first kernel using m_axi interface and input the second one using s_axilite, but the result is not what I’ve expected. I believe the first kernel is not giving the output at the end of the operations, but right at the begining.

Can anyone give me some help here?

Thank you very much


Do you need two kernels? Could you combine the code into one kernel?

If you have two separate kernels, you could use an AXI stream interface.


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Thank you. I have implemented using AXI stream interface and it works exactly as I want. I thought it could be a better way to pass a scalar value, but it works using AXI stream

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Could you share how to getting started with multi kernels and AXI stream? I want to learn it. Thank you.