PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

Building PYNQ Base from source targeting ZCU104 board

I have followed the instructions on how to build the PYNQ project from source on a learn page ( Tutorial: Rebuilding the PYNQ base overlay) but I get an error during the “vivado -mode batch -source build_bitstream.tcl -notrace”:

write_bitstream failed
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst ()
base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst ()
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

I am using the 2.4 version of PYNQ with Vivado 2018.3. This method works perfectly when I build from source for my Z1 board just not the ZCU104 board. Would anyone have some advice on how to overcome this issue?

Thanks!

You need a license for some of the IP used in this design.

If you are from a university, you can request a donation of this IP from the Xilinx University Program.
http://www.xilinx.com/university

If you just want to try it, you should also be able to use the evaluation licenses:

Cathal

Thanks for the suggestion. I have applied for access to the XUP.