Could not find IP or hierarchy LSTM_Top_0 in overlay

[shiqi17]

I checked the DMA with system ILA and found no error by design valid, I don’t know why the IP core of this LSTM is not connected

And the rest of the work keeps getting stuck here in dma.wait

[marioruiz]

Hi @shiqi17,

Only memory mapped IP will appear in the ip_dict. Your IP is AXI4-Stream, so it will not be displayed in the ip_dict.

Mario

[shiqi17]

My code executesdma.sendchannel.transfer(in_buf),
but it doesn’t dma.sendchannel.wait().Because I can print 1 and 2 but can’t print dma.sendchannel transfer completed ,like this picture. how to solve the problem? I need your help.

[shiqi17]

Or how can I be sure that the DMA data can be sent to the IP core and then sent out?

[shiqi17]

I REALLY NEED YOUR HELP!
When I use ‘‘overlay?’’ instruction ,I can’t find the LSTM_Top_0 IP.

Type: Overlay
String form: <pynq.overlay.Overlay object at 0xafe1f4f0>
File: /usr/local/lib/python3.6/dist-packages/pynq/overlay.py
Docstring:
Default documentation for overlay ./mnist_lstm.bit. The following
attributes are available on this overlay:

IP Blocks

axi_dma_0 : pynq.lib.dma.DMA

Hierarchies

None

Interrupts

None

GPIO Outputs

None
Class docstring:
This class keeps track of a single bitstream’s state and contents.

The overlay class holds the state of the bitstream and enables run-time
protection of bindlings.

Our definition of overlay is: “post-bitstream configurable design”.
Hence, this class must expose configurability through content discovery
and runtime protection.

The overlay class exposes the IP and hierarchies as attributes in the
overlay. If no other drivers are available the DefaultIP is constructed
for IP cores at top level and DefaultHierarchy for any hierarchies that
contain addressable IP. Custom drivers can be bound to IP and hierarchies
by subclassing DefaultIP and DefaultHierarchy. See the help entries
for those class for more details.

This class stores four dictionaries: IP, GPIO, interrupt controller
and interrupt pin dictionaries.

Each entry of the IP dictionary is a mapping:
‘name’ → {phys_addr, addr_range, type, config, state}, where
name (str) is the key of the entry.
phys_addr (int) is the physical address of the IP.
addr_range (int) is the address range of the IP.
type (str) is the type of the IP.
config (dict) is a dictionary of the configuration parameters.
state (str) is the state information about the IP.

Each entry of the GPIO dictionary is a mapping:
‘name’ → {pin, state}, where
name (str) is the key of the entry.
pin (int) is the user index of the GPIO, starting from 0.
state (str) is the state information about the GPIO.

Each entry in the interrupt controller dictionary is a mapping:
‘name’ → {parent, index}, where
name (str) is the name of the interrupt controller.
parent (str) is the name of the parent controller or ‘’ if attached
directly to the PS.
index (int) is the index of the interrupt attached to.

Each entry in the interrupt pin dictionary is a mapping:
‘name’ → {controller, index}, where
name (str) is the name of the pin.
controller (str) is the name of the interrupt controller.
index (int) is the line index.

Attributes

bitfile_name : str
The absolute path of the bitstream.
bitstream : Bitstream
The corresponding bitstream object.
ip_dict : dict
All the addressable IPs from PS. Key is the name of the IP; value is
a dictionary mapping the physical address, address range, IP type,
parameters, registers, and the state associated with that IP:
{str: {‘phys_addr’ : int, ‘addr_range’ : int, ‘type’ : str, ‘parameters’ : dict, ‘registers’: dict, ‘state’ : str}}.
gpio_dict : dict
All the GPIO pins controlled by PS. Key is the name of the GPIO pin;
value is a dictionary mapping user index (starting from 0),
and the state associated with that GPIO pin:
{str: {‘index’ : int, ‘state’ : str}}.
interrupt_controllers : dict
All AXI interrupt controllers in the system attached to
a PS interrupt line. Key is the name of the controller;
value is a dictionary mapping parent interrupt controller and the
line index of this interrupt:
{str: {‘parent’: str, ‘index’ : int}}.
The PS is the root of the hierarchy and is unnamed.
interrupt_pins : dict
All pins in the design attached to an interrupt controller.
Key is the name of the pin; value is a dictionary
mapping the interrupt controller and the line index used:
{str: {‘controller’ : str, ‘index’ : int}}.
Init docstring:
Return a new Overlay object.

An overlay instantiates a bitstream object as a member initially.

Parameters

bitfile_name : str
The bitstream name or absolute path as a string.
download : bool
Whether the overlay should be downloaded.
ignore_version : bool
Indicate whether or not to ignore the driver versions.

Note

This class requires a Vivado TCL file to be next to bitstream file
with same name (e.g. base.bit and base.tcl).

[marioruiz]

Hi,

@shiqi17

When I use ‘‘overlay?’’ instruction ,I can’t find the LSTM_Top_0 IP.

I have answer this here:

Could not find IP or hierarchy LSTM_Top_0 in overlay

Hi @shiqi17, Only memory mapped IP will appear in the ip_dict. Your IP is AXI4-Stream, so it will not be displayed in the ip_dict. Mario

I suggest you check out the DMA tutorials:

Tutorial: PYNQ DMA (Part 1: Hardware design)

PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. …

Mario

[shiqi17]

1.how could i detect if this ip core LSTM_top_0 has been successfully connected to the DMA？
2. I tried simulating this example and still don’t know how to solve it.My code stuck before “dam.sendchannel.wait”.Because it can print 1 and 2 but not “dma.sendchannel.wait”