Hello 
I need to learn how to use the DAC and ADC on a ZCU111 with Pynq.
I create a simple design with a DMA to be able to read data from RAM to AXIS DAC and to write AXIS ADC data to RAM.
More or less, it’s like Strathclyde’s QPSK project but very light and without QPSK.
If I succeed, I will share my work on GitHub. I think some people speak about a similar project here (RFSoC DAC with Pynq), but It never finished ?
You can found my Vivado project here : ZCU111-DAC-ADC-exemple.pdf (240.2 KB)
I add a constant for AXIS bus of write DMA, because usp_rf_data_converter IP not offer one.
My jupyter notebook can be found here : ZCU111-DAC-ADC-exemple.ipynb (4.2 KB)
Thank you very much
Damien
After reading a few documents, the constant is not a good idea.
It is necessary to have a TLAST port for the DMA, and the ADC did not provide it.
Probably it is necessary to use a custom IP to convert AXI STREAM without TLAST signal to AXI STREAM with TLAST signal ?
Damien
Hello,
I post the question on Xilinx forum, and I found the solution for the TLAST here : https://forums.xilinx.com/t5/Versal-and-UltraScale/TLAST-signal-with-Zynq-UltraScale-RFSoC-RFData-Converter-on/m-p/1156447#M14945
The DAC seem to work correctly but not the ADC for the moment.
Damien
Hi Damien,
Could you please share the .tcl script for your final vivado block design?
Sorry, can you share your bitstream and hwh file with the project?
Thank you Damien