i working with a ZCU111 (pynq firmware v2.7) board since several time but i’m not a real expert with SOC, now i’m in stuck because i’m trying to acquire a signal with the ADC on board (schematic here attached rfsoc.pdf (166.4 KB)
The signal generation with the DAC is working well and also the acquisition but only for the first 1024 byte (exactly the FIFO depth) after there is a sort of phase jump every beginning of 1024 new block.
Hi @marioruiz ,
thank you for replying me. I appreciate it. I saw that post but unfortunately i don’t have a good experience with FIFO and DMA transaction, could you explain me more in details?
Had read ij0r explain and sounds like a ping-pong buffer is more suitable.
His explanation simply said the next DMA request is not N but N-FIFO_SIZE.
But the final Stream_Size request is N, such that this cannot simply use default API to complete the job.
Hum, interesting that do the default IP from Vivado got IP could make this work w/o using HLS?