I am studying about the DPU System design. I have one concern about DPU-PYNQ and the reference design mentioned in PG338 (v3.3).
In DPU-PYNQ design, what is the role of AXI Interconnect blocks between the DPU and MPSoC? Meanwhile in the reference design, we can connect them directly?
Figure 1: DPU-PYNQ design
Figure 2: Reference design in PG338
Thank you in advance.
The interconnect block allows for multiple AXI connections to be connected. For example, in the DPU-PYNQ system, an interconnect is inserted to allow
M_AXI_HPM0_LPDto communicate with both
S_AXI_CONTROL of the DPU core and
S_AXI of a verification IP,
axi_vip_2. The interconnects wont change the functionality of how the system works, they are usually inserted automatically by the Vivado IPI connection automation.
The reference design from PG338 has exposed more AXI ports in the PS, which is configurable in the PS parameters. This might be why fewer interconnects were instantiated in that design.
All the best,
So clear. Thank you for the explanation.