Interface custom Verilog block with AXI GPIO IP

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1

Hi.
I need to run a fairly simple custom (but with lots of input bits) block using PYNQ, and i’d like to interface it via AXI. Now, I can make an AXI wrapper etc, but this means a bunch of text editing.
Does something prevents me from just using a bunch of “AXI GPIO” IPs for the cell’s inputs and outputs?
I know that those are meant to interface external pins, but it seems to work, at least for a simple clock divider cell:

gpio connectivity
gpio connectivity1374×467 95.8 KB

I would guess that the memory mapping will be rather wasteful, but other than that, any other reasoning against?

Thanks ahead!

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2

The design is okay, but if you meant to do clock division, why not use the Vivado clock wizard?

3

Hi, Thanks for the reply.
This block is a conceptual simple Verilog implementation (I’m also less familiar with Vivado’s wizard tools…). Eventually, I want to use the AXI-GPIO approach for other blocks as well, so this was more a conceptual question rather than a clock-divider implementation issue.
Confirming that there shouldn’t be an implementation issue helps a lot. Thanks!
M

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