I need to run a fairly simple custom (but with lots of input bits) block using PYNQ, and i’d like to interface it via AXI. Now, I can make an AXI wrapper etc, but this means a bunch of text editing.
Does something prevents me from just using a bunch of “AXI GPIO” IPs for the cell’s inputs and outputs?
I know that those are meant to interface external pins, but it seems to work, at least for a simple clock divider cell:
I would guess that the memory mapping will be rather wasteful, but other than that, any other reasoning against?