DMA fails after second read

after read DMA 2nd time


the idle never become True.
Was this caused by TLAST no exist in the bitstream?

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Hello @jetlan ,

the idle never become True.

If I remember well, it is due to your system not receiving as many data as expected.

Page 26 of PG021 confirms this in the reset bit description:

Soft reset for resetting the AXI DMA core. Setting this bit to a 1
causes the AXI DMA to be reset. Reset is accomplished gracefully.
Pending commands/transfers are flushed or completed.
AXI4-Stream outs are terminated early, if necessary with associated
TLAST. Setting either MM2S_DMACR.Reset = 1 or
S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After
completion of a soft reset, all registers and bits are in the Reset
• 0 = Reset not in progress. Normal operation.
• 1 = Reset in progress.

However, I am not aware of any information about tlast from the AXI_DMA IP. If you need it, you may want to make a small IP for this, which just sets a reset-able bit when tlast is encountered.


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Hello @cathalmccabe There is a problem. Can you suggest what I can do? Thanks for your time?

is the overlay already loaded? check the dma name on vivado project, is it same stated here?


thanks @mizan it’s not the same name it’s okay now , thank you

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