I managed to run this example on zcu111. Then I tried to replace the FIFO with a custom IP generated with AMD-Xilinx Model Composer. The first read just gets me zeros. The subsequent attempts for transfers or reads results errors. The error message was either “DMA transfer has not started” or the “DMA IP is not idle”. Has any one has managed to have a similar design? I carried the ‘tlast’ signal from input to output but no luck
Moving this to a new post. Could you please post more information about your design? It would help if you can share your block diagram, and HLS code and software versions.
Thanks @cathalmccabe for your interest.
An update: I managed to achieve some progress by propagating TLAST from the Master to Slave and feeding TREADY from Slave to Master of the DMA AXI-Stream. However, I see that in the beginning of a transfer there is a burst of 4 data cycles for 32-bit wide TDATA only the first 4 data words and the last (i.e. 15th) word arrive in order where the 4th to 14th words get replaced by 15th word. Has anyone else observed this?
AXI DMA LogiCORE IP Product Guide (PG021) states “Note: In the absence of any setup (that is, before it is programmed to run), AXI DMA will pull the s_axis_s2mm_tready signal Low after taking in four beats of streaming data. This will throttle the input data stream. To have a minimum amount of throttling, ensure that the AXI DMA is set up to run much before the actual data arrives.”
Is the only workaround to pad the send transfer with 16 dummy words and discard those in the received data?
How this is avoided in the AXI-DMA example?