AXI Stream IP doesn't work

Support
1

Hi @cathalmccabe
I created my IP using Verilog in vivado.
Below is my IP code.

module project_newpd#(parameter DATA_WIDTH = 64)(
input wire axi_clk,
input wire axi_reset_n,

input wire s_axis_valid,
input wire [DATA_WIDTH-1:0] s_axis_data,
output wire s_axis_ready,

output reg m_axis_valid,
output [31:0] m_axis_data,
input wire m_axis_ready
);

reg enab;
assign s_axis_ready = m_axis_ready;
    always @(axi_clk)
    begin
      if(axi_reset_n==1'b1)
      begin
      if(s_axis_valid & s_axis_ready)
        begin
          enab=1'b1;
        end
      end
    end
count mm(.clk(axi_clk),.res(axi_reset_n),.design_data(s_axis_data),.design_out(m_axis_data),.enab(enab));
always @(axi_clk) 
begin
    m_axis_valid <= s_axis_valid & s_axis_ready;  
end   

endmodule
2

Your code has what looks like mistakes, and none of these issues are related to PYNQ.

You only ever set enab and m_axis_valid and never reset them. How much data will this IP generate, and what do you expect to transfer in a DMA transaction? There is no way to determine this.

You also need TLAST if you are using the DMA.

You should try to read up about AXI streams.
I would suggest you use the “Create and Package New IP” tool in Vivado to create a template for your AXI stream peripheral.

Cathal

3

@cathalmccabe

This is getting very confusing:

Working non-working?
All these posts are related to the same issues?

Any of them really related to PYNQ image Python coding?

This sounds people is using PYNQ for Xilinx forum rather than PYNQ related questions.