Hi @cathalmccabe
I created my IP using Verilog in vivado.
Below is my IP code.
module project_newpd#(parameter DATA_WIDTH = 64)(
input wire axi_clk,
input wire axi_reset_n,
input wire s_axis_valid,
input wire [DATA_WIDTH-1:0] s_axis_data,
output wire s_axis_ready,
output reg m_axis_valid,
output [31:0] m_axis_data,
input wire m_axis_ready
);
reg enab;
assign s_axis_ready = m_axis_ready;
always @(axi_clk)
begin
if(axi_reset_n==1'b1)
begin
if(s_axis_valid & s_axis_ready)
begin
enab=1'b1;
end
end
end
count mm(.clk(axi_clk),.res(axi_reset_n),.design_data(s_axis_data),.design_out(m_axis_data),.enab(enab));
always @(axi_clk)
begin
m_axis_valid <= s_axis_valid & s_axis_ready;
end
endmodule