dear,
I use the dma to read the fifo data. The fifo data is written from other modules. The depth of the fifo is 1024.
When I create an xlnk with a depth of 10, I cannot read the complete ten data each time, only one data can be read.
The following is an example. At this time, fifo is full, and the data is 1 to 1024. When I want to read ten data for the first time, I can only read 1.
ad = dma_tutorial.dma_ad
ad_receive = xlnk.cma_array(shape=(10,), dtype=np.uint32)
ad.recvchannel.transfer(ad_receive)
ad.recvchannel.wait()
print(ad_receive)
[1 0 0 0 0 0 0 0 0 0]
1 Like
It seems that I sloved this problem.
In the previous version, the tlast and tvaild settings on the fifo slave side are the same. If I want to read 10 data, the remaining data can only be filled to 0
So I reread the AXI STREAM protocol, and redesign the tlast signal so that I can read multiple data at once through dma. Now whenever the tenth data is written, I will send a tlast signal.The following result graph shows that I can read 16 data at a time
As a result, it meets my needs without any mistakes. Iām not sure whether such a solution is correct, and it seems to be a problem about AXI STREAM protocol
