Dear all,
I am using Kria AI development kit with pynq 2.7.
I am trying to build base.bit for kria AI starter kit. I have been encountered with “ERROR: [HLS 200-1715] Encountered problem during source synthesis”. Does any one have more insights into it.
kindly find the terminal output here
harish@harish:~/Kria-PYNQ/kv260/base$ make
make -C …/…/pynq/boards/ZCU104/base/ hls_ip
make[1]: Entering directory ‘/home/harish/Kria-PYNQ/pynq/boards/ZCU104/base’
vivado -mode batch -source build_ip.tcl -notrace
****** Vivado v2021.1 (64-bit)
**** SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
**** IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source build_ip.tcl -notrace
Building color_convert_2 IP
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2021.1 (64-bit)
**** SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
**** IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /tools/Xilinx2021/Vitis_HLS/2021.1/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running ‘/tools/Xilinx2021/Vitis_HLS/2021.1/bin/unwrapped/lnx64.o/vitis_hls’
INFO: [HLS 200-10] For user ‘harish’ on host ‘harish’ (Linux_x86_64 version 5.4.0-122-generic) on Sun Aug 14 19:40:10 CEST 2022
INFO: [HLS 200-10] On os Ubuntu 18.04.4 LTS
INFO: [HLS 200-10] In directory ‘/home/harish/Kria-PYNQ/pynq/boards/ip/hls’
Sourcing Tcl script ‘color_convert_2/script.tcl’
INFO: [HLS 200-1510] Running: open_project color_convert_2
INFO: [HLS 200-10] Opening project ‘/home/harish/Kria-PYNQ/pynq/boards/ip/hls/color_convert_2’.
INFO: [HLS 200-1510] Running: set_top color_convert_2
INFO: [HLS 200-1510] Running: add_files color_convert_2/color_convert.cpp
INFO: [HLS 200-10] Adding design file ‘color_convert_2/color_convert.cpp’ to the project
INFO: [HLS 200-1510] Running: add_files -tb color_convert_2/color_convert_test.cpp
INFO: [HLS 200-10] Adding test bench file ‘color_convert_2/color_convert_test.cpp’ to the project
INFO: [HLS 200-1510] Running: open_solution solution1
INFO: [HLS 200-10] Opening solution ‘/home/harish/Kria-PYNQ/pynq/boards/ip/hls/color_convert_2/solution1’.
INFO: [SYN 201-201] Setting up clock ‘default’ with a period of 3.3ns.
INFO: [HLS 200-1611] Setting target device to ‘xczu7ev-ffvc1156-2-i’
INFO: [HLS 200-1505] Using flow_target ‘vivado’
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2021.1;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xczu7ev-ffvc1156-2-i
INFO: [HLS 200-1510] Running: create_clock -period 3.3
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 251.044 MB.
INFO: [HLS 200-10] Analyzing design file ‘color_convert_2/color_convert.cpp’ …
WARNING: [HLS 207-5528] Ignore interface attribute or pragma which is not used in top function: color_convert_2/color_convert.cpp:13:9
WARNING: [HLS 207-5301] unused parameter ‘print’: /tools/Xilinx2021/Vitis_HLS/2021.1/common/technology/autopilot/ap_int_base.h:792:16
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 4.52 seconds. CPU system time: 0.29 seconds. Elapsed time: 4.25 seconds; current allocated memory: 252.313 MB.
INFO: [HLS 200-777] Using interface defaults for ‘Vivado’ flow target.
ERROR: [HLS 200-1715] Encountered problem during source synthesis
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 7.24 seconds. CPU system time: 0.51 seconds. Elapsed time: 7.3 seconds; current allocated memory: 252.595 MB.
Pre-synthesis failed.
while executing
“source color_convert_2/script.tcl”
(“uplevel” body line 1)
invoked from within
"uplevel #0 [list source $arg] "
INFO: [HLS 200-112] Total CPU user time: 9.02 seconds. Total CPU system time: 0.89 seconds. Total elapsed time: 8.6 seconds; peak allocated memory: 252.313 MB.
INFO: [Common 17-206] Exiting vitis_hls at Sun Aug 14 19:40:19 2022…
child process exited abnormally
INFO: [Common 17-206] Exiting Vivado at Sun Aug 14 19:40:19 2022…
makefile:10: recipe for target ‘hls_ip’ failed
make[1]: *** [hls_ip] Error 1
make[1]: Leaving directory ‘/home/harish/Kria-PYNQ/pynq/boards/ZCU104/base’
Makefile:14: recipe for target ‘pynq_hls’ failed
make: *** [pynq_hls] Error 2
Kind regards
Harish