Export RTL: Failed to generate IP

Hello, I am having a problem exporting RTL from Vivado HLS 2019.1 just recently. The source code is for a PYNQ-Z2 board. I have been able to export the same source previously and it worked. I have already tried a different source code and still the same problem. Anyone knows how to fix this issue?
Below is the error message generated.

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This is a HLS problem, not a PYNQ issue.
You would be better posting this on the Xilinx forums.

If you check your project directory, there should be a log file with more info on the problem.


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Okay. Thank you for the response. :slight_smile:

Apply the patch : https://support.xilinx.com/s/article/76960

This one works. Thanks for the solution. :slight_smile:

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